Voltage Regulator (Regulatorctrl, Regulatorsel) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
Note: For the maximum permitted frequency, please see the data sheet.
Note: If prescaler source is selected to PLL output: Even though it is possible to select no
division ratio (:1) for the divide-by-C counter it is not recommended. The resulting
output clock will have an odd clock duty ratio (direct PLL output can have up to 90:10
duty). Always select at least a division ratio > 1.
Example:
The PLL x output should be used as prescaler clock source, which has in this example 128
MHz. The prescaler should output 16 MHz. All CAN clocks should be enabled.
#set PSCLOCKSOURCE PSCLOCK_PLL ;<<< 0x4C0h: CANPRE;
#set PSDVC
#set CANCLOCK

3.6 Voltage Regulator (REGULATORCTRL, REGULATORSEL)

With the following settings the behavior of the main-regulator and sub-regulator in the device
modes can be configured. The main-regulator can be enabled and disabled independently
for Sub-run and STOP/RTC and the sub regulator output voltage for sub-run and STOP/RTC
can be controlled.
The settings may depend on the configuration of the PLL frequency, the wait state settings
of the internal flash interface, the device and the access type. Therefore it is necessary to
check the data sheet.
The following table shows the settings for the main and the flash regulator of MB91F469G
for flash read. Please check the latest data sheet for later information.
Core Clock (CLKB)
to 20 MHz
to 32 MHz
to 44 MHz
to 48 MHz
to 88MHz
to 100MHz
Available settings for REGULATORCTRL (REGCTR):
- B'0 0 0 0 0 0 0 0
| | | | | | | |
| | | | | | | |_____ MAINDSBL
| | | | | | |_______ MAINKPEN
| | | | | |_________ Reserved
| | | | |___________ Reserved
| | | |_____________ MSTBO (read only)
| | |_______________ Reserved
| |_________________ Reserved
|___________________ Reserved
BIT[7:5]: Reserved
BIT[4]: MSTBO - Main regulator Standby output flag. (read only)
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
0x07 ;<<< 0x4C0h: CANPRE_DVC; => /8
0x00 ;<<< 0x4C1h: CANCKD; all CAN Clks enabled
1.8 V Operation of
main regulator and Flash?
Yes
Yes
Yes
No
Yes
No
- 23 -
=> PLLx ; 128 MHz
;
1.9 V Operation of
main regulator and Flash?
Yes
Yes
Yes
Yes
Yes
Yes
MCU-AN-300021-E-V10
16 MHz