User Clock Settings (Clockspeed == Clock_User) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)

3 User Clock Settings (CLOCKSPEED == CLOCK_USER)

Beside the default configurations with the settings for clocks and the related registers, there
is the possibility to define a user configuration for the settings. In the following the different
settings are explained. The following figure shows which part of the clock settings can be
configured in the start91460.asm.
Main Clock SV
Cntr.
Main Logic
Oscillator
1
4 MHz
0 CSVCR_
MSVE
Sub
Oscillator
Sub Clock SV
0
32 kHz
1
CSVCR_
SSVE
Cntr.
Logic
100 kHz
CSVCR
RC
Oscillator
0
1 CSCFG_
2 MHz
RCSEL
Source Oscillation Source Oscillation
Beside the clock settings the startup supports the settings for the voltage regulators and the
wait state settings of the internal flash, too. The clock modulator is not part of the user clock
settings, but part of the general settings.
The user clock settings can be found in the startup91460.asm in the chapter "5.1
CLOCKSPEED == CLOCK_USER".
MCU-AN-300021-E-V10
Start91460.asm
Configurable in Start91460.asm
1/2
PLL Interface x1, x2, ...x25
1/G
Auto-Gear
PLL
CLKVCO
x 1/M
1/N
FB CLKPLLFB
0
Multiplier
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
CSVCR_
SCKS
Clock Supervisor Clock Supervisor
Base Clock Generator Base Clock Generator
- 14 -
CLKPLL
Clock
0
1
Modulator 1
CMCR, CMPR 2
0
CMCR_ 3 CLKR_
FMOD CLKS
0
3
1 CANPRE_
CPCKS
Operating Clock Generator Operating Clock Generator CAN Clock Prescaler CAN Clock Prescaler
© Fujitsu Microelectronics Europe GmbH
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
Φ
Base Clock
Ext. Bus Clock
CLKT
Divider /1 .. /16
DIV1R
Peripheral Clock
CLKP
Divider /1 .. /16
DIV0R
CPU Clock
CLKB
Divider /1 .. /16
DIV0R
CAN Clock
CANCLK
Divider /1 .. /16
CANPRE