Clock Divider (Cpuclock, Perclock, Extbusclock) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)

3.4 Clock divider (CPUCLOCK, PERCLOCK, EXTBUSCLOCK)

The base clock can be divided for the different clock trees. There are clock divider for the
CPU clock (CLKB), the peripheral clock (CLKP) and the external bus interface clock (CLKT).
The divider can be configured independently.
Main Clock SV
Cntr.
Main Logic
Oscillator
1
4 MHz
0 CSVCR_
MSVE
Sub
Oscillator
Sub Clock SV
0
32 kHz
1
CSVCR_
SSVE
Cntr.
RC Logic
Oscillator
CSVCR
100 kHz
RC
0
Oscillator
2 MHz 1 CSCFG_
RCSEL
Available settings for CPUCLOCK (DIV0R_B), PERCLOCK (DIV0R_P), EXTBUSCLOCK
(DIV1R_T):
Name
BASECLOCK_DIV1
BASECLOCK_DIV2
BASECLOCK_DIV3
BASECLOCK_DIV4
BASECLOCK_DIV5
BASECLOCK_DIV6
BASECLOCK_DIV7
BASECLOCK_DIV8
BASECLOCK_DIV9
BASECLOCK_DIV10
BASECLOCK_DIV11
BASECLOCK_DIV12
BASECLOCK_DIV13
BASECLOCK_DIV14
BASECLOCK_DIV15
BASECLOCK_DIV16
Note: CPUCLOCK corresponds to the register DIV0R_B at the addresses 0x486h.
Note: PERCLOCK corresponds to the register DIV0R_P at the addresses 0x486h.
Note: EXTBUSCLOCK corresponds to the register DIV1R_T at the addresses 0x487h.
Note: Never exceed the maximum operation frequency. Check the corresponding data
sheet.
MCU-AN-300021-E-V10
Start91460.asm
1/2
PLL Interface x1, x2, ...x25
1/G
Auto-Gear
PLL
x CLKVCO 1/M
1/N
FB CLKPLLFB
0
Multiplier
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
CSVCR_
SCKS
Setting
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
CLKPLL
Clock
0
1
Modulator 1
CMCR, CMPR 2
0
CMCR_ 3
FMOD
0
3
1 CANPRE_
CPCKS
Remark
clock = 1/1 base clock
clock = 1/2 base clock
clock = 1/3 base clock
clock = 1/4 base clock
clock = 1/5 base clock
clock = 1/6 base clock
clock = 1/7 base clock
clock = 1/8 base clock
clock = 1/9 base clock
clock = 1/10 base clock
clock = 1/11 base clock
clock = 1/12 base clock
clock = 1/13 base clock
clock = 1/14 base clock
clock = 1/15 base clock
clock = 1/16 base clock
- 20 - © Fujitsu Microelectronics Europe GmbH
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
Φ
Base Clock
Ext. Bus Clock
CLKT
Divider /1 .. /16
DIV1R
Peripheral Clock
CLKR_
CLKP
CLKS
Divider /1 .. /16
DIV0R
CPU Clock
CLKB
Divider /1 .. /16
DIV0R
CAN Clock
CANCLK
Divider /1 .. /16
CANPRE