Quectel QuecOpen AG525R-GL Hardware Design page 61

3.14. SPI Interfaces
The module provides two SPI interfaces supporting only master mode. The maximum clock frequency of
SPI is up to 50 MHz.
Table 20: Pin Definition of SPI Interfaces
Pin Name Pin No.
SPI1_CLK 216
SPI1_CS 213
SPI1_MISO 219
SPI1_MOSI 210
SPI2_CLK 103
SPI2_CS 105
SPI2_MISO 106
SPI2_MOSI 108
The following figure shows the timing relationship of SPI interfaces. The related parameters of SPI timing
are shown in the table below.
AG525R-GL_QuecOpen_Hardware_Design
I/O Description
DO SPI1 clock
DO SPI1 chip select
DI SPI1 master-in salve-out
DO SPI1 master-out slave-in
DO SPI2 clock
DO SPI2 chip select
DI SPI2 master-in salve-out
DO SPI2 master-out slave-in
Figure 26: SPI Timing
Automotive Module Series
AG525R-GL QuecOpen Hardware Design
Comment
1.8 V power domain.
Can be configured to GPIO.
If unused, keep them open.
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