Quectel QuecOpen AG525R-GL Hardware Design page 56

Table 13: Pin Definition of UART1 Interface
Pin Name Pin No.
UART1_CTS 71
UART1_RTS 74
UART1_TXD 70
UART1_RXD 72
Table 14: Pin Definition of BT UART Interface
Pin Name Pin No.
BT_UART_TXD 59
BT_UART_RXD 63
BT_UART_RTS 61
BT_UART_CTS 62
Table 15: Pin Definition of Debug UART Interface
Pin Name Pin No.
DBG_TXD 107
DBG_RXD 110
Table 16: Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
AG525R-GL_QuecOpen_Hardware_Design
I/O Description
DO UART1 clear to send
DI UART1 request to send
DO UART1 transmit
DI UART1 receive
I/O Description
DO BT UART transmit
DI BT UART receive
DI BT UART request to send
DO BT UART clear to send
I/O Description
DO Debug UART transmit
DI Debug UART receive
Min.
-0.3
1.17
0
1.35
Automotive Module Series
AG525R-GL QuecOpen Hardware Design
Comment
1.8 V power domain.
Can be configured to GPIOs.
Comment
1.8 V power domain.
Can be configured to GPIOs
Comment
1.8 V power domain.
1.8 V power domain.
Max.
0.63
2.1
0.45
1.8
Unit
V
V
V
V
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