Quectel QuecOpen AG525R-GL Hardware Design page 57

The module provides 1.8 V UART interfaces. A level translator should be used if customers' application is
equipped with a 3.3 V UART interface. A level translator TXS0104E-Q1 provided by Texas Instruments
(visit http://www.ti.com for more information) is recommended. The following figure shows a reference
design.
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.
NOTES
1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps.
2. For the purpose of reducing power consumption, it is recommended to switch off the power supply for
VDD_1V8 in sleep mode.
3. Please note that the module CTS is connected to the host CTS, and the module RTS is connected to
the host RTS.
AG525R-GL_QuecOpen_Hardware_Design
Figure 22: Reference Circuit with Translator Chip
Figure 23: Reference Circuit with Transistor Circuit
Automotive Module Series
AG525R-GL QuecOpen Hardware Design
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