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Quectel EC2 Series Design Manualline

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EC2x&EG2x-G Series
PCB Design Guideline
LTE Standard Module Series
Rev.Quectel_EC2x&EG2x-G_Series_PCB_Design_Guideline_V1.0
Date: 2020-07-23
Status: Released
www.quectel.com

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  • Page 1 EC2x&EG2x-G Series PCB Design Guideline LTE Standard Module Series Rev.Quectel_EC2x&EG2x-G_Series_PCB_Design_Guideline_V1.0 Date: 2020-07-23 Status: Released www.quectel.com...
  • Page 2 QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION.

  • Page 3: About The Document

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline About the Document Revision History Version Date Author Description 2020-07-23 Lim PENG Initial EC2x&EG2x-G_Series_PCB_Design_Guideline 2 / 37...

  • Page 4: Table Of Contents

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Contents About the Document ..........................2 Contents ..............................3 Table Index ..............................4 Figure Index ..............................5 Introduction ............................6 1.1. Applicable Modules ........................6 1.2. Safety Information ........................7 PCB Design Overview ........................8 2.1.
  • Page 5 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Table Index Table 1: Applicable Modules ........................6 Table 2: Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB Structures ................................31 Table 3: Related Documents ........................36 Table 4: Terms and Abbreviations ......................
  • Page 6 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Figure Index Figure 1: Overview of TE-A 1st Layer ......................8 Figure 2: High-priority Signals to Be Designed (TE-A 1st Layer) ..............9 Figure 3: DC-DC Converter (EVB 4th Layer) and Module Interfaces On TE-A (EVB 1st Layer) ....10 Figure 4: VBAT Traces (TE-A 1st Layer) ....................

  • Page 7: Introduction

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Introduction This document mainly introduces the PCB reference design for Quectel LTE Standard EC2x&EG2x-G series modules, and it takes EC25-TE-A, FC20-TE-A and UMTS&LTE EVB as examples. 1.1. Applicable Modules Table 1: Applicable Modules...

  • Page 8: Safety Information

    EC2x&EG2x-G series modules. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.

  • Page 9: Pcb Design Overview

     A 4-layer PCB is strongly recommended.  First, check whether the module’s footprint is of the latest version provided by Quectel. For specific footprint of each module, please refer to document [1], [2], [3] or [4].  Do not design pads 73–84 and do not route the keepout area with any traces or copper.

  • Page 10: Design Priorities And Considerations For Pcb Traces

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 2.2. Design Priorities and Considerations for PCB Traces 2.2.1. Design Priorities Design priorities of PCB traces in order:  Antenna traces.  High-speed signal (SGMII, SDIO and USB) traces.  Power supply (VBAT_BB, VBAT_RF, USIM_VDD, SDIO_VDD, VDD_EXT) traces. ...

  • Page 11: Interface Design

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Interface Design 3.1. Power Supply 3.1.1. DC-DC Converter  DC-DC converter should be away from the sensitive signal traces such as SDIO, USB, SGMII, audio and RF. If possible, shield DC-DC converter with shielding cover and reserve spacing for shielding frame.

  • Page 12: Vbat

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.1.2. VBAT  Place 100 μF, 100 nF, 33 pF and 10 pF capacitors for both VBAT_BB and VBAT_RF respectively. The smaller the capacitance is, the closer the compositors are to the two VBAT pins. ...
  • Page 13 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline  TVS for VBAT should be placed close to module’s pin VBAT_BB and VBAT_RF.  VBAT traces should be away from sensitive signal traces such as SDIO, USB, SGMII, USB audio and RF to avoid paralleling or crossing with them.

  • Page 14: Pwrkey & Reset_N

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.2. PWRKEY & RESET_N  PWRKEY and RESET_N signal traces are recommended to be surrounded with ground.  If filter capacitors for PWRKEY and RESET_N are required, put them near the two pins. PWRKEY RESET Figure 8: PWRKEY and RESET_N Traces (TE-A 1st Layer)

  • Page 15: Usb Interface

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.3. USB Interface 3.3.1. USB_DM & USB_DP Signals  The spacing between USB_DP/USB_DM and other signal traces should be greater than 0.5 mm, maintaining the integrity of the reference plane and avoiding crossing with signal lines on adjacent layers.
  • Page 16 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline USB_DM/DP USB_DM/DP Figure 11: Overview of USB_DM/DP Signal Traces (EVB 3rd Layer) EC2x&EG2x-G_Series_PCB_Design_Guideline 15 / 37...

  • Page 17: Usb_Vbus Signal

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.3.2. USB_VBUS Signal USB_VBUS is a USB detection signal, with maximum current of 1 mA. In general, a trace width of 0.1 mm is sufficient. TE-A TE-A interface interface USB_VBUS USB_VBUS Test Test points...

  • Page 18: Ethernet Phy

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.4. Ethernet PHY 3.4.1. SGMII Interface  Signal traces of SGMII_MCLK, SGMII_MDATA, EPHY_RST_N and EPHY_INT_N should be surrounded with ground.  The spacing between SGMII_TX_M/SGMII_TX_P/SGMII_RX_M/SGMII_RX_P lines should be at least 3 times wider than the traces, and that between the SGMII signal trace and other signal traces should also be at least 3 times wider than SGMII traces.
  • Page 19 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline SGMII_RST SGMII_TX_M SGMII_INT SGMII_TX_P SGMII_DATA SGMII_RX_P SGMII_CLK SGMII_RX_M Figure 15: Overview of SGMII Signal Traces (TE-A 3rd Layer) EC2x&EG2x-G_Series_PCB_Design_Guideline 18 / 37...

  • Page 20: Ethernet Components

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.4.2. Ethernet Components A four-layer PCB should be used when using the SGMII interface to implement the Ethernet function in the application.  The first layer is for non-sensitive traces and 1.1 V power supply traces. ...

  • Page 21: Audio Interfaces

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline DVDD_1V1 is output by AR8033’s LX pin through an LC circuit. The 4.7 μH inductor in the LC circuit should be able to provide 1 A current with low direct current resistance. The trace width for the inductor is recommended to be at least 1 mm.

  • Page 22: Codec & Microphone & Speaker

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline PCM_CLK PCM_SYNC PCM_OUT PCM_IN Figure 19: Overview of PCM Signal Traces (TE-A 3rd Layer) 3.5.2. Codec & Microphone & Speaker The codec should be kept away from interference sources such as high-power components, power sources, CPU, DRAM, Flash, PMU, LCD, RF antennas and other high-frequency components, isolated, and close to one of the edges or corners of the board, and could be shielded if there is sufficient space.
  • Page 23 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline ALC5616 Figure 20: Overview of Codec ALC5616 (EVB 1st Layer)  Keep the traces for microphone and speaker as short as possible. For MIC signals, it is recommended to design differential pairs. ...

  • Page 24: Sd Card Interface

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline SPK1_P SPK1_M Speaker Amplifier MIC_P MIC_N MIC1_N MIC1_P SPK2_M SPK2_P Handset Application SPK_L Earphone SPK_R application AGND MIC2_P Figure 21: Overview of Analog Audio Signal Traces (EVB 1st Layer) 3.6. SD Card Interface ...
  • Page 25 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline SD Card connector SD Card connector TVS & Capacitors & Resistors TVS & Capacitors & Resistors SD card traces SD card traces Figure 22: Overview of SD Card Signal Traces (EVB 1st Layer) SD_CLK SD_CMD VDD_SDIO...

  • Page 26: Wlan Interface

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.7. WLAN Interface  Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc, as well as noisy signals such as clock and DC-DC signals, etc. ...
  • Page 27 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline SD_CLK SD_CLK SD_CMD SD_DATA SD_CMD SD_DATA VDD_1V8 VDD_1V8 Figure 25: Overview of SDIO Signal Traces (FC20 TE-A 3rd Layer) EC2x&EG2x-G_Series_PCB_Design_Guideline 26 / 37...

  • Page 28: U)Sim Interface

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.8. (U)SIM Interface  The total length of each (U)SIM signal trace should be less than 200 mm.  Isolate USIM_CLK and USIM_DAT with ground plane to avoid the interference between each other. ...

  • Page 29: Adc Interface

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.9. ADC Interface All ADC signal traces should be surrounded with ground. ADC1 ADC0 Figure 28: Overview of ADC Signal Traces (EVB 3rd Layer) EC2x&EG2x-G_Series_PCB_Design_Guideline 28 / 37...

  • Page 30: Gpios

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.10. GPIOs  Keep GPIO traces away from interference signals such as clock, RF and power supplies, etc.  Filter capacitors need to be added and be placed close to the module when GPIO is used as the input.

  • Page 31: Antenna Interfaces

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.11. Antenna Interfaces 3.11.1. PCB Structures of Microstrip And Coplanar Waveguide 3.11.1.1. PCB Structure of Microstrip Waveguide Figure 30: PCB Structure of Microstrip Waveguide 3.11.1.2. PCB Structure of Coplanar Waveguide Factors affecting impedance include dielectric constant (usually 4.2–4.6, here 4.4), dielectric layer height (H), RF trace width (W), the spacing between RF traces and the ground (S) and copper thickness (T).
  • Page 32 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Figure 31: PCB Structure of Coplanar Waveguide Table 2: Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB Structures Dielectric Height (H) RF Trace Width (W) Spacing Between RF Trace and The Ground (S) 0.076 mm 0.1188...

  • Page 33: Reference Design Of Rf Layout

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline 3.11.2. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S).

  • Page 34: Pcb Layout Considerations Of Coplanar Waveguide

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) 3.11.3. PCB Layout Considerations of Coplanar Waveguide There are 6 guidelines of the PCB layout should be taken into consideration.
  • Page 35 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Leave a small keepout area for the RF traces on the top layer to reduce parasitic effects. Keep the traces as short as possible. Avoid right-angle routing for RF traces and 135 degrees is recommended when traces turn corner.

  • Page 36: Thermal Design

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Thermal Design For more details of the thermal design of the PCB, please refer to document [5]. EC2x&EG2x-G_Series_PCB_Design_Guideline 35 / 37...

  • Page 37: Appendix References

    LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline Appendix References Table 3: Related Documents Document Name Remark Quectel_EC21_Footprint&Part EC21 series Footprint&Part Quectel_EC25_Footprint&Part EC25 series Footprint&Part Quectel_EC20_R2.1_Footprint&Part EC20 R2.1 Footprint&Part Quectel_EG25-G&EG21-G_Footprint&Part EG25-G&EG21-G Footprint&Part Thermal design guide for LTE standard, Quectel_LTE_Module_Thermal_Design_Guide LTE-A and Automotive modules Table 4: Terms and Abbreviations Abbreviation...
  • Page 38 LTE Standard Module Series EC2x&EG2x-G Series PCB Design Guideline SGMII Serial Gigabit Media Independent Interface Universal Serial Bus (U)SIM (Universal) Subscriber Identity Module VBAT Voltage at Battery WLAN Wireless Local Area Network EC2x&EG2x-G_Series_PCB_Design_Guideline 37 / 37...

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