Xilinx KCU1250 User Manual page 61

#PMBUS
set_property PACKAGE_PIN E15
set_property IOSTANDARD
set_property PACKAGE_PIN B15
set_property IOSTANDARD
set_property PACKAGE_PIN A15
set_property IOSTANDARD
set_property PACKAGE_PIN N27
set_property IOSTANDARD
set_property PACKAGE_PIN M20
set_property IOSTANDARD
set_property PACKAGE_PIN L20
set_property IOSTANDARD
set_property PACKAGE_PIN R21
set_property IOSTANDARD
set_property PACKAGE_PIN R22
set_property IOSTANDARD
set_property PACKAGE_PIN K16
set_property IOSTANDARD
set_property PACKAGE_PIN K15
set_property IOSTANDARD
set_property PACKAGE_PIN K18
set_property IOSTANDARD
set_property PACKAGE_PIN K17
set_property IOSTANDARD
#UART
set_property PACKAGE_PIN B14
set_property IOSTANDARD
set_property PACKAGE_PIN A14
set_property IOSTANDARD
set_property PACKAGE_PIN C14
set_property IOSTANDARD
set_property PACKAGE_PIN D14
set_property IOSTANDARD
#USB_GPIOs
set_property PACKAGE_PIN F14
set_property IOSTANDARD
set_property PACKAGE_PIN G14
set_property IOSTANDARD
set_property PACKAGE_PIN J14
set_property IOSTANDARD
set_property PACKAGE_PIN J15
set_property IOSTANDARD
#MGTs
set_property PACKAGE_PIN N29
set_property PACKAGE_PIN N30
set_property PACKAGE_PIN R29
set_property PACKAGE_PIN R30
set_property PACKAGE_PIN K31
set_property PACKAGE_PIN K32
set_property PACKAGE_PIN J33
set_property PACKAGE_PIN J34
set_property PACKAGE_PIN M31
set_property PACKAGE_PIN M32
set_property PACKAGE_PIN L33
set_property PACKAGE_PIN L34
KCU1250 User Guide
UG1057 (v1.0) December 19, 2014
Appendix Appendix C: Master Constraints File Listing
[get_ports "DUT_PMBUS_ALERT"]
LVCMOS18 [get_ports "DUT_PMBUS_ALERT"]
[get_ports "DUT_PMBUS_CLK"]
LVCMOS18 [get_ports "DUT_PMBUS_CLK"]
[get_ports "DUT_PMBUS_DATA"]
LVCMOS18 [get_ports "DUT_PMBUS_DATA"]
[get_ports "DUT_SMAP_CSI_B"]
LVCMOS18 [get_ports "DUT_SMAP_CSI_B"]
[get_ports "DUT_SMAP_D4"]
LVCMOS18 [get_ports "DUT_SMAP_D4"]
[get_ports "DUT_SMAP_D5"]
LVCMOS18 [get_ports "DUT_SMAP_D5"]
[get_ports "DUT_SMAP_D6"]
LVCMOS18 [get_ports "DUT_SMAP_D6"]
[get_ports "DUT_SMAP_D7"]
LVCMOS18 [get_ports "DUT_SMAP_D7"]
[get_ports "DUT_FREQ_CLK"]
LVCMOS18 [get_ports "DUT_FREQ_CLK"]
[get_ports "DUT_FREQ_DATA"]
LVCMOS18 [get_ports "DUT_FREQ_DATA"]
[get_ports "DUT_FREQ_BSY"]
LVCMOS18 [get_ports "DUT_FREQ_BSY"]
[get_ports "DUT_FREQ_RDY"]
LVCMOS18 [get_ports "DUT_FREQ_RDY"]
[get_ports "UART_TXD_O"]
LVCMOS18 [get_ports "UART_TXD_O"]
[get_ports "UART_RXD_I"]
LVCMOS18 [get_ports "UART_RXD_I"]
[get_ports "UART_RTS_O_B"]
LVCMOS18 [get_ports "UART_RTS_O_B"]
[get_ports "UART_CTS_I_B"]
LVCMOS18 [get_ports "UART_CTS_I_B"]
[get_ports "UART_GPIO_0"]
LVCMOS18 [get_ports "UART_GPIO_0"]
[get_ports "UART_GPIO_1"]
LVCMOS18 [get_ports "UART_GPIO_1"]
[get_ports "UART_GPIO_2"]
LVCMOS18 [get_ports "UART_GPIO_2"]
[get_ports "UART_GPIO_3"]
LVCMOS18 [get_ports "UART_GPIO_3"]
[get_ports "131_REFCLK1_P"]
[get_ports "131_REFCLK1_N"]
[get_ports "131_REFCLK0_P"]
[get_ports "131_REFCLK0_N"]
[get_ports "131_TX3_P"]
[get_ports "131_TX3_N"]
[get_ports "131_RX3_P"]
[get_ports "131_RX3_N"]
[get_ports "131_TX2_P"]
[get_ports "131_TX2_N"]
[get_ports "131_RX2_P"]
[get_ports "131_RX2_N"]
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