Xilinx KCU1250 User Manual page 33

The information for each GTH transceiver clock input is shown in
Table 1-16: GTH Transceiver Reference Clock Inputs
U1 FPGA Pin
R30
R29
N30
N29
L30
L29
J30
J29
AF5
AF6
AD5
AD6
AB5
AB6
Y5
Y6
V5
V6
T5
T6
P5
P6
M5
M6
K5
K6
H5
H6
KCU1250 User Guide
UG1057 (v1.0) December 19, 2014
Net Name Quad
131_REFCLK0_N
131_REFCLK0_P
131_REFCLK1_N
131_REFCLK1_P
132_REFCLK0_N
132_REFCLK0_P
132_REFCLK1_N
132_REFCLK1_P
224_REFCLK0_N
224_REFCLK0_P
224_REFCLK1_N
224_REFCLK1_P
225_REFCLK0_N
225_REFCLK0_P
225_REFCLK1_N
225_REFCLK1_P
226_REFCLK0_N
226_REFCLK0_P
226_REFCLK1_N
226_REFCLK1_P
227_REFCLK0_N
227_REFCLK0_P
227_REFCLK1_N
227_REFCLK1_P
228_REFCLK0_N
228_REFCLK0_P
228_REFCLK1_N
228_REFCLK1_P
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Chapter 1: KCU1250 Board Features and Operation
Connector
224 J37
224 J37
224 J37
224 J37
225 J38
225 J38
225 J38
225 J38
226 J39
226 J39
226 J39
226 J39
227 J40
227 J40
227 J40
227 J40
228 J41
228 J41
228 J41
228 J41
229 J42
229 J42
229 J42
229 J42
230 J43
230 J43
230 J43
230 J43
Table 1-16.
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