SMART Embedded Computing MVME4100 Programmer's Reference Manual page 53

Table 4-1
MPC8548E
Signal
LBCTL, LALE,
LGPL2
LGPL3, LGPL5
MSRCID0
MSRCID1
MVME4100 Single Board Computer Programmer's Reference (6806800H19D)
MPC8548E POR Configuration Settings (continued)
Default
Select
POR
Option
Setting
Resistors 101
Fixed 11
Fixed 1
Fixed 1
Description State of Bit vs. Function
e500 core 000
clock PLL ratio
001
(e500
core:CCB
010
clock)
011
100
101
110
111
Boot 00
sequencer
01
configuration
10
11
Memory debug 0
configuration
1
DDR debug 0
configuration
1
Programming Details
4:1
9:2 (4.5:1)
1:1
3:2 (1.5:1)
2:1
5:2 (2.5:1)
3:1
7:2 (3.5:1)
Reserved
Boot sequencer enabled with
normal I2C address mode
Boot sequencer enabled with
extended I2C address mode
Boot sequencer disabled
Debug info from the LBC is
driven on MSRCID and
MDVAL pins
Debug info from the DDR
SDRAM controller is driven
on MSRCID and MDVAL pins
Debug info on ECC pins
instead of normal ECC
ECC pins function in normal
mode
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