Table 3-10 Pci Bus 2 Status Register - SMART Embedded Computing MVME4100 Programmer's Reference Manual

PCI_1_SPD
PCIX_1
PCI_1_64B
RSVD
Table 3-10
REG
BIT
Field
OPER
RESET
PCI_2_SPD
PCIX_2
PCI_2_64B
5.0V_VIO
3.3V_VIO
MVME4100 Single Board Computer Programmer's Reference (6806800H19D)
PCI Bus 1 Speed. Indicates the frequency of PCI bus 1.
00: 33 MHz
01: 66 MHz
10: 100 MHz
11: 133 MHz
PCI-X Bus 1. A set condition indicates that bus 1 is operating in PCI-X mode.
Cleared indicates PCI mode.
PCI Bus 1 64-bit. A set condition indicates that bus 1 is enabled to operate in
64-bit mode. Cleared indicates 32-bit mode.
Reserved for future implementation.
PCI Bus 2 Status Register
PCI Bus 2 Status Register - 0xF200 0009
7 6 5
3.3V_VIO 5.0V_VIO RSVD
R R R
X X X
PCI Bus 2 Speed. Indicates the frequency of PCI bus 2.
00: 33 MHz
01: 66 MHz
10: 100 MHz
11: 133 MHz
PCI-X Bus 2. A set condition indicates that bus 2 is operating in PCI-X mode.
Cleared indicates PCI mode.
PCI Bus 2 64-bit. A set condition indicates that bus 2 is enabled to operate in 64-
bit mode. Cleared indicates 32-bit mode.
5.0V VIO Enabled. This bit set indicates that the PMC bus (PCI Bus 2) is
configured for 5.0V VIO.
3.3V VIO Enabled. This bit set indicates that the PMC bus (PCI Bus 2) is
configured to 3.3V VIO.
Register Descriptions
4 3
RSVD PCI_2_64B
R R
0 1
2 1 0
PCIX_2 PCI_2_SPD
R R R
X X X
33