Table of Contents
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Register Descriptions
Table 3-1
Address
F200 0016
F200 0017
F200 0018
F200 0019
F200 001A
F200 001B
F200 001C
F200 001D
F200 001E
F200 001F
F200 0020
F200 0021
F200 0022
F200 0023
F200 0024
F200 0025
F200 0026 -
F200 0027
F200 0028
F200 002C
F200 0030
F200 0031
F200 0032
F200 0033
F200 0034
F200 0038
24
System I/O Memory Map (continued)
Definition
Reserved
Reserved
NAND Flash Chip 2 Control Register
NAND Flash Chip 2 Select Register
Reserved
Reserved
NAND Flash Chip 2 Presence Register
NAND Flash Chip 2 Status Register
Reserved
Reserved
Watch Dog Timer Load
Reserved
Reserved
Reserved
Watchdog Control
Watchdog Resolution
Watchdog Count
Reserved (32 bits)
Reserved (32 bits)
PLD Revision
Reserved
Reserved
Reserved
PLD Date Code (32 bits)
Test Register 1 (32 bits)
MVME4100 Single Board Computer Programmer's Reference (6806800H19D)
Register Descriptions
LBC Bank/
Notes
Chip Select
4
1
4
1
4
3
4
3
4
1
4
1
4
3
4
3
4
1
4
1
4
3
4
1
4
1
4
1
4
3
4
4
4
1
4
1
4
3
4
1
4
1
4
1
4
3
4
3
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