Pld Revision Register; Pld Date Code Register; Table 3-25 Pld Date Code Register - SMART Embedded Computing MVME4100 Programmer's Reference Manual

Register Descriptions
3.1.21

PLD Revision Register

The MVME4100 provides a PLD revision register that can be read by the system software
to determine the current revision of the timers/registers PLD.
Table 3-24
REG
BIT
Field
OPER
RESET
PLD_RE
V
3.1.22

PLD Date Code Register

The MVME4100 PLD provides a 32-bit register which contains the build date code of the
timers/registers PLD.
Table 3-25
REG
BIT
Field
OPER
RESET
yy
mm
dd
vv
42
PLD Revision Register
PLD Revision Register - 0xF200 0030
7 6 5
PLD_REV
R
01
8-bit field containing the current timer/register PLD revision. The revision
number starts with 01.
PLD Date Code Register
Date Code Register 1 - 0xF200 0034
31:24 23:16
yy mm
R
xxxx
Last two digits of year
Month
Day
Version of the day
MVME4100 Single Board Computer Programmer's Reference (6806800H19D)
4 3 2
15:8
dd
Register Descriptions
1 0
7:0
vv