3.1.4
NOR Flash Control/Status Register
The MVME4100 Flash Control/Status Register provides software controlled bank write
protect and map select functions as well as boot block select, bank write protect, and
activity status for the NOR flash.
Table 3-5
REG
BIT
Field
OPER
RESET
FLASH_RDY
FBT_BLK_SEL
F_WP_HW
F_WP_SW
MAP_SEL
RSVD
MVME4100 Single Board Computer Programmer's Reference (6806800H19D)
NOR Flash Control/Status Register
NOR Flash Control/Status Register - 0xF200 0003
7
6
5
RSVD
RSVD
RSVD
R
R
R
0
0
0
Flash Ready. This bit provides the current state of the NOR flash devices
Ready/Busy# pins. These open drain output pins from each flash device are wire
OR'd to form Flash Ready. Refer to the appropriate flash device data sheet for a
description on the function of the Ready/Busy# pin.
Flash Boot Block Select. This bit reflects the current state of the Boot Block B
Select switch. A cleared condition indicates that boot block A is selected and
mapped to the highest address. A set condition indicates that boot block B is
selected and mapped to the highest address (see
Hardware Flash Bank Write Protect switch status. This bit reflects the current
state of the FLASH BANK WP switch. A set condition indicates that the NOR
Flash bank is write protected. A cleared condition indicates that the flash bank is
not write protected.
Software Flash Bank Write Protect. This bit provides software-controlled
protection against inadvertent writes to the flash memory devices. A set condition
indicates that the entire flash is write-protected. A cleared condition indicates that
the flash bank is not write-protected, only when the HW write-protect bit is not set.
This bit is set during reset and must be cleared by the system software to enable
writing of the flash devices.
Memory Map Select. When this bit is cleared, the flash memory map is controlled
by the Flash Boot Block Select switch (see the MVME4100 Installation and Use
manual for switch settings). When the Map Select bit is set, boot block A is
selected and mapped to the highest address (see
Reserved for future implementation.
Register Descriptions
4
3
2
MAP_S
F_WP_
F_WP_
EL
SW
HW
R/W
R/W
R
0
1
X
Figure 3-1
Figure 3-1
1
0
FBT_BL
FLASH
K_SEL
_RDY
R
R
X
1
).
).
29
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