3.1.18 Watch Dog Control Register; 3.1.19 Watch Dog Timer Resolution Register - SMART Embedded Computing MVME4100 Programmer's Reference Manual

Register Descriptions

3.1.18 Watch Dog Control Register

The MVME4100 provides a watch dog timer control register.
Table 3-21
REG
BIT
Field
OPER
RESET
SYSRST
EN
RSVD

3.1.19 Watch Dog Timer Resolution Register

The MVME4100 provides a watch dog timer resolution register.
Table 3-22
REG
BIT
Field
OPER
RESET
RES
40
Watch Dog Timer Control Register
Watch Dog Timer Control Register - 0xF200 0024
7 6 5
EN SYS RSVD
RST
R/W R
0 0 0
System Reset. If cleared a board-level reset is generated when a time-out occurs. If
set, a VMEbus SYSRST is generated when a time-out occurs. If MVME4100 is
SYSCON then a local reset will also result in a VMEbus SYSRST.
Enable. If cleared the watch dog timer is disabled. If set the watch dog timer is
enabled.
Reserved for future implementation.
Watch Dog Timer Resolution Register
Watch Dog Timer Resolution Register - 0xF200 0025
7 6 5
RSVD RSVD RSVD
R
0 0 0
Resolution. These bits define the resolution of the counter.
2 s
0:
4 s
1:
8 s
2:
16 s
3:
MVME4100 Single Board Computer Programmer's Reference (6806800H19D)
4 3 2
RSVD RSVD RSVD
0 0 0
4 3 2
RSVD RES
R/W
0 9
Register Descriptions
1 0
RSVD RSVD
0 0
1 0