Xilinx LogiCore PLB PCI Full Bridge Specification page 8

PLB PCI Full Bridge (v1.00a)
Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields
0xFE35FEDC on the PLB bus.
Table 1: PLB PCI Bridge Interface Design Parameters
Generic
G1 Number of IPIF devices
G2 IPIF device 0 BAR
IPIF BAR high address
G3
0
PCI BAR to which IPIF
BAR 0 is mapped
G4 unless
C_INCLUDE_BAROFF
SET_REG = 1
IPIF BAR 0 memory
G5
designator
G6 IPIF device 1 BAR
IPIF BAR high address
G7
1
PCI BAR to which IPIF
BAR 1 is mapped
G8 unless
C_INCLUDE_BAROFF
SET_REG = 1
IPIF BAR 1 memory
G9
designator
G10 IPIF device 2 BAR
IPIF BAR high address
G11
2
PCI BAR to which IPIF
BAR 2 is mapped
unless
G12
C_INCLUDE_BAROFF
SET_
REG = 1
8
Feature / Parameter
Description Name
Bridge Features Parameter Group
C_IPIFBAR
_NUM
C_IPIFBAR_0
C_IPIFBAR_
HIGHADDR_0
C_IPIFBAR2
PCIBAR_0
C_IPIF_SPACE
TYPE_0
C_IPIFBAR_1
C_IPIFBAR_
HIGHADDR_1
C_IPIFBAR2
PCIBAR_1
C_IPIF_SPACE
TYPE_1
C_IPIFBAR_2
C_IPIFBAR_
HIGHADDR_2
C_IPIFBAR2
PCIBAR_2
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Allowable Values
1-6; Parameters listed
below corresponding to
unused BARs are
ignored, but must be
valid values. BAR label
0 is the required bar for
all values 1-6 and the
index increments from 0
as BARs are added
(1)
Valid PLB address
(1)
Valid PLB address
Vector of length
1
C_PLB_AWIDTH
0 = I/O space
1 = Memory space
(1)
Valid PLB address
(1)
Valid PLB address
Vector of length
C_PLB_AWIDTH
0 = I/O space
1 = Memory space
(1)
Valid PLB address
(1)
Valid PLB address
Vector of length
C_PLB_AWIDTH
Default VHDL
Value Type
6 integer
std_logic_
0xFFFFFFFF
vector
std_logic_
0x00000000
vector
std_logic_
0xFFFFFFFF
vector
1 integer
std_logic_
0xFFFFFFFF
vector
std_logic_
0x00000000
vector
std_logic_
0xFFFFFFFF
vector
1 integer
std_logic_
0xFFFFFFFF
vector
std_logic_
0x00000000
vector
std_logic_
0xFFFFFFFF
vector
DS508 March 21, 2006
Product Specification