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Xilinx LogiCore PLB PCI Full Bridge Specification page 16

Xilinx inc. plb pci full bridge product specification

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PLB PCI Full Bridge (v1.00a)
Table 2: PLB PCI Bridge I/O Signals (Contd)
Port
CBE[(C_PCI_DBUS_WI
P55
DTH/8)-1:0]
P56
PAR
P57
FRAME_N
P58
DEVSEL_N
P59
TRDY_N
P60
IRDY_N
P61
STOP_N
P62
IDSEL
P63
INTR_A
P64
PERR_N
P65
SERR_N
P66
REQ_N
P67
GNT_N
P68
RST_N
P69
PCLK
P70
REQ_N_toArb
P71
FRAME_I
16
Signal Name
Interface
PCI Bus
PCI Bus
PCI Transaction Control Signals
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus
PCI Bus Internal Arbiter Signals
Internal
Internal
I/O
I/O
Time-multiplexed bus command and byte enable bus
Generates and checks even parity across AD and
I/O
CBE
I/O
Driven by an initiator to indicate a bus transaction
Indicates that a target has decoded the address
I/O
presented during the address phase and is claiming
the transaction
Indicates that the target is ready to complete the
I/O
current data phase
Indicates that the initiator is ready to complete the
I/O
current data phase
Indicates that the target has requested to stop the
I/O
current transaction
Indicates that the interface is the target of a
I
configuration cycle
PCI Interrupt Signals
Indicates that LogiCORE PCI interface requests an
O
interrupt
PCI Error Signals
Indicates that a parity error was detected while the
I/O
LogiCORE PCI interface was the target of a write
transfer or the initiator of a read transfer
Indicates that a parity error was detected during an
I/O
address cycle, except during special cycles
PCI Arbitration Signals
Indicates to the arbiter that the LogiCORE PCI
O
initiator requests access to the bus
Indicates that the arbiter has granted the bus to the
I
LogiCORE PCI initiator
PCI System Signals
PCI bus reset signal is used to bring PCI-specific
I
registers, sequences, and signals to a consistent
state
I
PCI bus clock signal
Input from PCI Bus REQ_N available at top-level as
O
output from bridge
Input from PCI Bus FRAME_N availalble at top-level
O
as output from bridge
www.xilinx.com
Description
DS508 March 21, 2006
Product Specification

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