Xilinx LogiCore PLB PCI Full Bridge Specification page 10

PLB PCI Full Bridge (v1.00a)
Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic
IPIF BAR to which PCI
G27 BAR 0
is mapped
Power of 2 in the size in
G28 bytes of PCI BAR 0
space
IPIF BAR to which PCI
G29
BAR 1 is mapped
Power of 2 in the size in
G30 bytes of PCI BAR 1
space
IPIF BAR to which PCI
G31
BAR 2 is mapped
Power of 2 in the size in
G32 bytes of PCI BAR 2
space
G33 PCI address bus width
G34 PCI data bus width
Both PCI2IPIF FIFO
address bus widths.
G35 Usable depth is
2^C_PCI2IPIF_FIFO_A
BUS_WIDTH - 3
Both IPIF2PCI FIFO
address bus widths.
G36 Usable depth is
2^C_IPIF2PCI_FIFO_A
BUS_WIDTH - 3
Include explicit
instantiation of INTR_A
G37
io-buffer (must be 1 to
include io-buffer)
Include explicit
instantiation of REQ_N
G38
io-buffer (must be 1 to
include io-buffer)
Minimum PCI2IPIF
FIFO occupancy level
that triggers the bridge
G39
to initiate a prefetch PCI
read of a remote PCI
agent
10
Feature / Parameter
Description Name
C_PCIBAR2
IPIFBAR_0
C_PCIBAR_
LEN_0
C_PCIBAR2IPI
FBAR_1
C_PCIBAR_
LEN_1
C_PCIBAR2
IPIFBAR_2
C_PCIBAR_
LEN_2
C_PCI_ABUS_
WIDTH
C_PCI_DBUS_
WIDTH
C_PCI2IPIF_
FIFO_ABUS_
WIDTH
C_IPIF2PCI_
FIFO_ABUS_
WIDTH
C_INCLUDE_
INTR_A_BUF
C_INCLUDE_
REQ_N_BUF
C_TRIG_PCI_
READ_OCC_
LEVEL
www.xilinx.com
Allowable Values
Vector of length
0x00000000
C_PLB_AWIDTH
5 to 29
Vector of length
0x00000000
C_PLB_AWIDTH
5 to 29
Vector of length
0x00000000
C_PLB_AWIDTH
5 to 29
32
32
4-14
4-14
0 = not included
1 = included
0 = not included
1 = included
5 to the lesser of 24 or
the PCI2IPIF FIFO
DEPTH-3. PCI2IPIF
FIFO DEPTH given by
2^C_PCI2IPIF_FIFO_
ABUS_WIDTH
Default VHDL
Value Type
std_logic_
vector
16 integer
std_logic_
vector
16 integer
std_logic_
vector
16 integer
32 integer
32 integer
9 integer
9 integer
1 integer
1 integer
32 integer
DS508 March 21, 2006
Product Specification