Xilinx LogiCore PLB PCI Full Bridge Specification page 14

PLB PCI Full Bridge (v1.00a)
PLB PCI Bus Interface I/O Signals
The I/O signals for the PLB PCI Bridge are listed in
shown in Figure 1
Table 2: PLB PCI Bridge I/O Signals
Port
P1 IP2INTC_Irpt
P2 PLB_Clk
P3 PLB_Rst
PLB_ABus(0:C_PLB_
P4
AWIDTH-1)
P5 PLB_PAValid
PLB_masterID(0:C_PLB
P6
_MID_WIDTH-1)
P7 PLB_abort
P8 PLB_RNW
PLB_BE(0:[C_PLB_DWI
P9
DTH/8]-1)
P10 PLB_MSize(0:1)
P11 PLB_size(0:3)
P12 PLB_type(0:2)
PLB_wrDBus(0:C_PLB_
P13
DWIDTH-1)
P14 PLB_wrBurst
P15 PLB_rdBurst
P16 Sl_addAck
P17 Sl_SSize(0:1)
P18 Sl_wait
P19 Sl_rearbitrate
P20 Sl_wrDAck
P21 Sl_wrComp
P22 Sl_wrBTerm
Sl_rdDBus(0:C_PLB_D
P23
WIDTH-1)
P24 Sl_rdWdAddr(0:3)
P25 Sl_rdDAck
P26 Sl_rdComp
14
in the PLB PCI Bridge block diagram.
Signal Name Interface
Internal
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
Table 2. The interfaces referenced in this table are
I/O
System Signals
O Interrupt from IP to the Interrupt Controller
PLB Signals
I PLB main bus clock. See table note 1.
I PLB main bus reset. See table note 1.
I Note 1 applies from P4 to P53.
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
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Description
DS508 March 21, 2006
Product Specification