Xilinx LogiCore PLB PCI Full Bridge Specification page 26

PLB PCI Full Bridge (v1.00a)
Table 8: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus) (Contd)
Bit(s) Name
PLB Master
25 Write Master
PLB Master
26 Write Target
Abort
PLB Master
27
Write PERR
PLB Master
28
Write SERR
PLB Master
29 Read Target
Abort
PLB Master
30
Read PERR
PLB Master
31
Read SERR
Bridge Interrupt Enable Register Description
The PLB PCI Bridge has interrupt enable features
Architecture. Bit assignment in the Bridge Interrupt Enable Register is shown in
enable register is read/write. All bits are cleared upon reset.
Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s) Name
0-18
PCI Initiator
19
Write SERR
PCI Initiator
20
Read SERR
21 Reserved
PLB Master
22 Write Retry
Timeout
26
Access
Read/Write
1 to clear
Abort
Read/Write
1 to clear
Read/Write
1 to clear
Read/Write
1 to clear
Read/Write
1 to clear
Read/Write
1 to clear
Read/Write
1 to clear
Reset
Access
Value
Read
Read/Write
Read/Write
Read/Write
Reset
Value
PLB Master Write Master Abort- Interrupt(25) indicates
that the PLB PCI Bridge asserted a PCI master abort due to
0x0
no response from a target.
PLB Master Write Target Abort- Interrupt(26) indicates a
PCI target abort occurred during a PLB Master Write to a
0x0
PCI target.
PLB Master Write PERR- Interrupt(27) indicates a PERR
0x0
error is detected on a PLB Master write to a PCI target.
PLB Master Write SERR- Interrupt(28) indicates that a
SERR error was detected by the v3.0 core when performing
0x0
as a PCI initiator writing data to a PCI target.
PLB Master Read Target Abort- Interrupt(29) indicates
that a target abort was detected by the v3.0 core when
0x0
performing as a PCI initiator reading data from a PCI target.
PLB Master Read PERR- Interrupt(30) indicates that a
PERR was detected by the v3.0 core when performing as a
0x0
PCI initiator reading data from a PCI target.
PLB Master Read SERR- Interrupt(31) indicates that a
SERR error was detected by the v3.0 core when performing
0x0
as a PCI initiator reading data from a PCI target.
as described in IPSPEC048 PLB Device Interrupt
Unassigned-
0x0
PCI Initiator Write SERR Enable- Enables this interrupt to
be passed to the interrupt controller.
0x0
• 0 - Not enabled.
• 1 - Enabled.
PCI Initiator Read SERR Enable- Enables this interrupt to
be passed to the interrupt controller.
0x0
• 0 - Not enabled.
• 1 - Enabled.
• Reserved
0x0
PLB Master Burst Write Retry Timeout Enable- Enables
this interrupt to be passed to the interrupt controller.
0x0
• 0 - Not enabled.
• 1 - Enabled.
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Description
Table 9. The interrupt
Description
DS508 March 21, 2006
Product Specification