Xilinx LogiCore PLB PCI Full Bridge Specification page 33

Table 15: Translation Table for PLB transactions to PCI commands (Contd)
Sequential Read, 4, 8 and
16-word cacheline read
Single Write (<=8 bytes)
Write Burst transfer double
word
Sequential fill, 4, 8 and
16-word cacheline write
Notes:
1. The PLB IPIF aligns the address on the IPIC to a double word boundary which is then presented on the PCI
bus. This is independent of the target word presented.
2. The 405 always sources the first word on the line (i.e., sequential fill) on write.
Table 16: Translation Table for PCI commands to PLB transactions
PCI Initiator Command
I/O Read
I/O Write
Memory Read
Memory Read Multiple
Memory Read Line
Memory Write
(single data phase)
Memory Write
(multiple data phase)
Memory Write Invalidate
Notes:
1. The PLB does not support dynamic byte enable (BE) in burst read transactions so when Memory Read Multiple
is translated to a PLB burst read, all BE are asserted during the PLB read operation.
2. The PLB does not support dynamic byte enable (BE) in burst write transactions so when Memory Write Multiple
is translated to a PLB burst write, all BE are asserted during the PLB write operation.
For all the transactions listed above, the following design requirements are specified:
• Both PCI and PLB clocks will be independent global buffers. For Virtex-4, RCLK must also be
driven by global buffer.
• The PLB clock can be slower or faster than the PCI clock. For Virtex-4, RCLK must be 200 MHz.
• Address space on the PCI side accessible from the PLB side must be translated to a 2
block on the PLB side. Up to six independent blocks are possible. Each block has parameters for
base address (BAR), high address which must define a 2
memory designator (memory or I/O).
• All address space on the PLB side that is accessible from the PCI side must be translated to a
maximum of three 2
possible because the LogiCore PCI v3.0 core supports up to 3 BARs. Each block has parameters for
length which must be a 2
of PCI memory space is supported. Space type is mirrored in the PCI configuration registers.
DS508 March 21, 2006
Product Specification
I/O Read
(1)
I/O Write
I/O Write
I/O Write
(2)
PLB Memory Prefetchable
Not Supported
Not Supported
PLB Single Read
PLB Burst Read with all BE asserted
PLB Single Read
PLB Single Write
2
PLB Burst Write of length defined by
available data in FIFO
PLB Burst Write
N
contiguous blocks on the PCI side. Up to three independent blocks are
N
range, and address translation vector. Only memory space in the sense
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PLB PCI Full Bridge (v1.00a)
Memory Read Multiple
Memory Write
Memory Write (multiple
data phase)
Memory Write (multiple
data phase)
PLB Memory Non-prefetchable
Not Supported
Not Supported
Not Supported
(1)
Not Supported
Not Supported
Not Supported
Not Supported
(2)
Not Supported
N
range, address translation vector, and
Not Supported
Not Supported
Not Supported
Not Supported
N
contiguous
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