Xilinx LogiCore PLB PCI Full Bridge Specification page 12

PLB PCI Full Bridge (v1.00a)
Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic
Number of IDELAY
G50 controllers instantiated.
Ignored it not Virtex-4
Includes IDELAY
primitive on GNT_N.
G51
Set by tcl-scripts and
ignored if not Virtex-4.
Provides a means for
BSB to pass LOC
coordinates for
IDELAYCTRLs for a
given board to
G52 EDK and is optional for
user to set LOC
constraints. This
parameter has no
impact on bridge
functionality.
PCI Configuration
G53 Space Header Device
ID
PCI Configuration
G54 Space Header Vendor
ID
PCI Configuration
G55 Space Header Class
Code
PCI Configuration
G56
Space Header Rev ID
PCI Configuration
G57 Space Header
Subsystem ID
PCI Configuration
G58 Space Header
Subsystem Vendor ID
PCI Configuration
G59 Space Header
Maximum Latency
PCI Configuration
G60 Space Header
Minimum Grant
12
Feature / Parameter
Description Name
C_NUM_
IDELAYCTRL
C_INCLUDE_
GNT_DELAY
C_IDELAY
CTRL_LOC
v3.0 Core Parameters Group
C_DEVICE_ID
C_VENDOR_
ID
C_CLASS_
CODE
C_REV_ID
C_SUB
SYSTEM_ID
C_SUBSYSTE
M_VENDOR_
ID
C_MAX_LAT
C_MIN_GNT
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Allowable Values
2-6
(Virtex-4 only)
1=Include IDELAY
primitive
(Virtex-4 only)
0=No IDELAY primitive
See Device
Implementation section,
subsection Virtex-4
Support for allowed
values
16-bit vector
16-bit vector
24-bit vector
8-bit vector
16-bit vector
16-bit vector
8-bit vector
8-bit vector
Configuration
Default VHDL
Value Type
2 integer
0 integer
NOT_SET string
std_logic_
0x0000
vector
std_logic_
0x0000
vector
std_logic_
0x000000
vector
std_logic_
0x00
vector
std_logic_
0x0000
vector
std_logic_
0x0000
vector
std_logic_
0x0F
vector
std_logic_
0x04
vector
DS508 March 21, 2006
Product Specification