Xilinx LogiCore PLB PCI Full Bridge Specification page 13

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic
Include configuration
G61 functionality via IPIF
transactions
Number of IDSEL
G62
signals supported
PCI address bit that PCI
G63 v3.0 core IDSEL is
connected to
PLB master ID bus
G64 width (set automatically
by XPS)
Number of masters on
G65 PLB bus (set
automatically by XPS)
G66 PLB Address width
G67 PLB Data width
Specifies the target
G68
technology
Notes:
1. The range specified must comprise a complete, contiguous power of two range, such that the range = 2
the n least significant bits of the Base Address are zero.
2. The minimum address range specified by C_BASEADDR and C_HIGHADDR must be at least 0x1FF.
C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BASEADDR + 1.
DS508 March 21, 2006
Product Specification
Feature / Parameter
Description Name
C_INCLUDE_
PCI_CONFIG
C_NUM_
IDSEL
C_BRIDGE_
IDSEL_ADDR_
BIT
IPIF Parameters Group
C_PLB_MID_
WIDTH
C_PLB_NUM_
MASTERS
C_PLB_
AWIDTH
C_PLB_
DWIDTH
C_FAMILY
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PLB PCI Full Bridge (v1.00a)
Allowable Values
0 = Not included
1 = Included
1 to 16
31 down to 16
Must be <= 15 +
C_NUM_IDSEL.
AD(31 down to 0) index
labeling
log (C_PLB_NUM_MA
2
STERS)
1-16
32 (only allowed value
64 (only allowed value
See PLB IPIF data
sheet
Default VHDL
Value Type
1 integer
8 integer
16 integer
3 integer
8 integer
32 integer
64 integer
virtex2 string
n
and
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