Xilinx LogiCore PLB PCI Full Bridge Specification page 24

PLB PCI Full Bridge (v1.00a)
Register and Parameter Dependencies
The addressable registers in the PLB PCI Bridge depend on the parameter settings shown in
Table 6: Register and Parameter Dependencies
Device Interrupt Status Register (ISR)
Device Interrupt Pending Register (IPR)
Device Interrupt Enable Register (IER)
Device Interrupt ID (IID)
Global Interrupt Enable Register (GIE)
Bridge Interrupt Register
Bridge Interrupt Enable Register
Reset Module
Configuration Address Port
Configuration Data Port
Bus Number/Subordinate Bus Number
IPIFBAR2PCIBAR_0 High-Order Bits
IPIFBAR2PCIBAR_1 High-Order Bits
IPIFBAR2PCIBAR_2 High-Order Bits
IPIFBAR2PCIBAR_3 High-Order Bits
IPIFBAR2PCIBAR_4 High-Order Bits
IPIFBAR2PCIBAR_5 High-Order Bits
Host Bridge Device Number
PLB PCI Bridge Interrupt Registers Descriptions
The interrupt module registers are always included in the bridge.
Interrupt Module Specifications
The interrupt registers are in the interrupt module that is instantiated in the IPIF module of the PLB PCI
Bridge. Details on the IPIF interrupt module including discussion of ISR, IPR, IER and IID are in the
PLB IPIF Interrupt Product Specification
24
Register Name
in the
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Parameter Dependence
Always present
Always present
Always present
Always present
Always present
Always present
Always present
Always present
Present only if G61=1
Present only if G61=1
Present only if G61=1
Present only if G48=1
Present only if G1>1 and G48=1
Present only if G1>2 and G48=1
Present only if G1>3 and G48=1
Present only if G1>4 and G48=1
Present only if G1=6 and G48=1
Present only if G49=1
Processor IP Reference Guide.
Table 6.
DS508 March 21, 2006
Product Specification