Xilinx LogiCore PLB PCI Full Bridge Specification page 21

Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)
Generic
C_NUM_PCI_RETRIES_IN
G43
_WRITES
C_NUM_PCI_PRDS_BET
G44 WN_RETRIES_IN_
WRITES
C_NUM_IPIF_RETRIES_
G45
IN_WRITES
G46 C_BASEADDR
G47 C_HIGHADDR
C_INCLUDE_BAROFFSET
G48
_REG
C_INCLUDE_DEVNUM_
G49
REG
G50 C_NUM_IDELAYCTRL
G51 C_INCLUDE_GNT_DELAY
G52 C_IDELAYCTRL_LOC
G53 C_DEVICE_ID
G54 C_VENDOR_ID
G55 C_CLASS_CODE
G56 C_REV_ID
G57 C_SUBSYSTEM_ID
C_SUBSYSTEM_VENDOR
G58
_ID
G59 C_MAX_LAT
G60 C_MIN_GNT
C_INCLUDE_PCI_
G61
CONFIG
DS508 March 21, 2006
Product Specification
Parameter Affects
G47
G46
G4, G8,
G12, G16,
G20 and
G24
G63
v3.0 Core Parameters Group
Configuration
G62, G63,
P62
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PLB PCI Full Bridge (v1.00a)
Depends Description
G46 to G47 define range in PLB-memory
G47 space that is responded to by PLB PCI
bridge register address space
G46 to G47 define range in PLB-memory
G46 space that is responded to by PLB PCI
bridge register address space
If G48=1, G4, G8, G12, G16, G20 and
G1 G24 have no meaning. The number of
registers included is set by G1
If G61=0, G49 has no meaning. If G49
and G61=1, G63 has no meaning.
G61, G62
Meaningful bits in the Device Number
register are defined by G62
If G68 ≠ Virtex-4, G50 has no meaning
G68
If G68 ≠ Virtex-4, G51 has no meaning
G68
If G68 ≠ Virtex-4, G52 has no meaning. If
G50 and G68=Virtex-4, G52 must include the
G68 number of LOC coordinates specified by
G50
If G61=1, signal P62 has an internal
connection and the top-level port P62
has no internal connection
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