Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic
PCI2IPIF FIFO
occupancy level in
double words that
G40
triggers the bridge to
initiate an IPIF burst
write to remote PLB
device
IPIF2PCI FIFO
occupancy level that
starts data transfer
(Both as initiator and
G41
target on PCI) to PCI
agent with multiple data
phases per transfer
(must meet 16 PCI
period maximum).
Minimum IPIF2PCI
FIFO occupancy level
that triggers bridge to
G42
initiate a prefetch IPIF
read of a remote PLB
slave
Number of PCI retry
G43
attempts in IPIF
posted-write operations
Number of PCI clock
periods between retries
G44
in posted- write
operations
Number of IPIF retry
attempts in
G45
posted-write PCI
initiator operations
G46
Device base address
Device absolute high
G47
address
Include the registers for
high-order bits to be
G48
substituted in
translation
Include the register for
local bridge device
number when
G49
configuration
functionality
(C_INCLUDE_PCI_CO
NFIG =1) is included
DS508 March 21, 2006
Product Specification
Feature /
Parameter
Description
Name
C_TRIG_IPIF_
WRBURST_
OCC_LEVEL
C_TRIG_PCI_
DATA_XFER_
OCC_LEVEL
C_TRIG_IPIF_
READ_OCC_
LEVEL
C_NUM_PCI_R
ETRIES_IN_
WRITES
C_NUM_PCI_P
RDS_BETWN_
RETRIES_IN_
WRITES
C_NUM_IPIF_
RETRIES_IN_
WRITES
C_BASE
ADDR
C_HIGHADDR
C_INCLUDE_
BAROFFSET_
REG
C_INCLUDE_D
EVNUM_REG
www.xilinx.com
PLB PCI Full Bridge (v1.00a)
Allowable Values
2 to the lesser of 24 or
the PCI2IPIF FIFO
DEPTH-3. PCI2IPIF
FIFO DEPTH given by
2^C_PCI2IPIF_FIFO_A
BUS_WIDTH
2 to the lesser of 24 or
the IPIF2PCI FIFO
DEPTH-3. IPIF2PCI
FIFO DEPH given by
2^C_IPIF2PCI_FIFO_
ABUS_WIDTH
2 to the lesser of 24 or
the IPIF2PCI FIFO
DEPTH-3. IPIF2PCI
FIFO DEPH given by
2^C_IPIF2PCI_FIFO_
ABUS_WIDTH
Any integer
Any integer
Any integer
(1), (2)
Valid PLB address
0xFFFFFFFF
(1), (2)
Valid PLB address
0x00000000
1 = include
0 = exclude
1 = include
0 = exclude
Default
VHDL
Value
Type
8
integer
8
integer
16
integer
3
integer
6
integer
6
integer
std_logic_
vector
std_logic_
vector
0
integer
0
integer
11
Need help?
Do you have a question about the LogiCore PLB PCI Full Bridge and is the answer not in the manual?
Questions and answers