Xilinx LogiCore PLB PCI Full Bridge Specification page 27

Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus) (Contd)
Bit(s) Name
PLB Master
23 Write Retry
Disconnect
PLB Master
24
Write Retry
PLB Master
25 Write Master
Abort
PLB Master
26 Write Target
Abort
PLB Master
27
Write PERR
PLB Master
28
Write SERR
PLB Master
29 Read Target
Abort
PLB Master
30
Read PERR
PLB Master
31
Read SERR
PLB PCI Bridge Reset Register Description
The IP Reset module is always instantiated in the PLB PCI Bridge. Details on the IPIF Reset module can
be found in the
PCI Bridge, independently of other modules in the system. The MIR is not included.
DS508 March 21, 2006
Product Specification
Reset
Access
Value
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Read/Write
0x0
Processor IP Reference Guide. The IP Reset module permits the software reset of the PLB
PLB Master Burst Write Retry Disconnect Enable-
Enables this interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Write Retry Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Write Master Abort Enable- Enables this
interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Write Target Abort Enable- Enables this
interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Write PERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Write SERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Read Target Abort Enable- Enables this
interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Read PERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
PLB Master Read SERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
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PLB PCI Full Bridge (v1.00a)
Description
27