ST STM32L152-EVAL User Manual page 17

UM1018
Figure 5.
MCU mode
IDD_CNT_EN (PB15)
Q12 = LOW_POWER_EN
(T4 pin 3)
Q13 = IDD_WAKEUP
(PC13)
Q13n = disconnect filter
(U7 pin 4)
Note:
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STM32L152-EVAL IDD low power modes measurement timing diagram
Run
3
0 ms
The principle used to measure a current when the STM32L is in Low power mode is:
1. Configure ADC to measure voltage on the IDD_Measurement pin (PA5).
2. Configure PA0 to serve as wakeup pin.
3. Enter Low power mode after setting IDD_CNT_EN signal low.
4. IDD_WAKEUP rising edge wakes up the MCU after around 300 ms.
5. Start ADC conversion as soon as possible after wakeup in order to measure the
voltage corresponding to Low power mode on capacitor C25.
6. Reset the counter by programming IDD_CNT_EN high (in less than 70 ms after the
wakeup) to avoid the R35 (1 KOhm) resistor being connected later in Run mode.
In Low power modes, the 1 KOhm resistor is connected when T4 goes off after entering Low
power mode. Q12 output of the counter allows connection of the 1 K resistor when the
current IDD becomes very low.
Figure 5 shows how the counter and T4 ensure that, 150 ms after IDD_CNT_EN falling
edge, the shunt resistor R35 is connected between VDD_MCU and the power supply in
order to reduce the measurement range to 30 uA full scale when VDD = 1.8 V.
Then after another 150 ms for current stabilization, R35 is shorted, the IDD measurement is
stored in C25, and the MCU is woken up.
After wakeup the MCU can measure the IDD current corresponding to the Low power mode
stored in C25.
It is recommended to maintain VDD on the STM32L at a value lower than 3.5 V during low
power current measurement to avoid extra current consumption on the NRST pin (U11 pin
14).
The reason for this is that the NRST pin of the STM32L is connected to the ST-LINK MCU
T_NRST signal (U23 pin 18), and as the ST-LINK is powered at 3.3 V a leakage current is
injected into the STM32L NRST pin when MCU VDD becomes equal to or greater than
3.5 V.
Wake-up
period
Wake-up
event
Stop or Standby
150 ms
Doc ID 18141 Rev 1
Hardware and layout
IDD
measurement
Clear CNT
event
5
6
4
300 ms
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