Software-Selectable Byte-Swapping Hardware; Byte-Ordering Schemes - Xycom XVME-653 Manual

XVME-653/658 Manual

Software-Selectable Byte-Swapping Hardware

Software-selectable byte-swapping hardware is integrated into all XVME-658 and
XVME-653/31x boards (see Table 1-1) to allow for the difference between the Intel and
Motorola byte-ordering schemes, allowing easy communication over the VMEbus. The
byte-swapping package incorporates several buffers either to pass data straight through
or to swap the data bytes as they are passed through.

Byte-Ordering Schemes

The Motorola family of processors stores data with the least significant byte located at
the highest address and the most significant byte at the lowest address. This is referred to
as a big-endian bus and is the VMEbus standard. The Intel family of processors—which
includes the AMD-K6 processors as well as the Intel Pentium processors—stores data in
the opposite way, with the least significant byte located at the lowest address and the
most significant byte located at the highest address. This is referred to as a little-endian
(PCI) bus. This fundamental difference is illustrated in Figure 4-1, which shows a 32-bit
quantity stored by both architectures, starting at address M.
The two architectures differ only in the way in which they store data into
memory, not in the way in which they place data on the shared data bus.
The XVME-653/658 contains a Universe chip that performs address-invariant translation
between the PCI bus (Intel architecture) and the VMEbus (Motorola architecture), and
byte-swapping hardware to reverse the Universe chip byte-lane swapping. (Contact Tun-
dra at www.tundra.com for a .pdf version of the Universe II manual.) Figure 4-2 shows
address-invariant translation between a PCI bus and a VMEbus.
4-12
Address
INTEL
Low Byte M
M+1
M+2
High Byte M+3
Figure 4-1 Byte Ordering Schemes
Note
MOTOROLA
High Byte
Low Byte