Vmebus Interrupt Handling - Xycom XVME-653 Manual

The address mode and type are programmed on a VMEbus slave image basis. The VME-
bus memory address location for the VMEbus slave cycle is specified by the Base and
Bound address. The PCI address is calculated by adding the Base address to the Transla-
tion offset address.
The XVME-653/658 DRAM memory is based on the PC architecture and is not contigu-
ous. The VMEbus slave images may be set up to allow this DRAM to appear as one
contiguous block.
In Compatible Mode, the first VMEbus slave image will have the Base and Bound reg-
ister set to 640 KB by the BIOS. For example:
VMEbus Slave Image 0 BS= 0000000h BD= A0000h TO = 0000000h
The second VMEbus slave image will have the Base register set to be contiguous with
the Bound register from the first VMEbus Slave image by the BIOS. The Bound register
is limited by the total XVME-653/658 DRAM. The Translation Offset register is offset
by 384 KB, which is equivalent to the A0000h-FFFFFh range on the XVME-653/658
board. For example:
VMEbus Slave Image 1 BS=A0000h BD= 400000h TO = 060000h
Mapping defined by the PC architecture can be overcome if the VMEbus Slave image
window is always configured with a 1 MB Translation Offset. From a user and software
standpoint, this is desirable because the interrupt vector table, system parameters, and
communication buffers (keyboard) are placed in low DRAM. This provides more system
protection.
When setting up slave images, the address and other parameters should
be set first. Only after the VMEbus slave image is set up correctly
should the VMEbus slave image be enabled. If a slave image is going to
be remapped, disable the slave image first, and then reset the address.
After the image is configured correctly, re-enable the image.
The VMEbus slave cycle becomes a master cycle on the PCI bus. The PCI bus arbiter is
the TSC chip. It arbitrates between the various PCI masters, the Pentium CPU, and the
Local bus IDE bus mastering controller. Because the VMEbus cannot be retried, all
VMEbus slave cycles must be allowed to be processed. This becomes a problem when a
PCI cycle to a PCI slave image is in progress while a VMEbus slave cycle to the onboard
DRAM is in progress. The PCI cycle will not give up the PCI bus and the VMEbus slave
cycle will not give up the VMEbus, causing the XVME-653/658 to become deadlocked.
If the XVME-653/658 is to be used as a master and a slave at the same time, the VME-
bus master cycles must obtain the VMEbus prior to initiating VMEbus cycles.
All VMEbus slave interface cycles are byte-swapped to maintain address coherency. For
more information on the Xycom Automation software selectable byte-swapping hard-
ware on the XVME-658 and the XVME-653/31x modules, refer to p. 4-12.

VMEbus Interrupt Handling

The XVME-653/658 can service VME IRQ[7:1]. A register in the Universe chip enables
the interrupt levels that will be serviced by the XVME-653/658. When a VMEbus IRQ is
asserted, the Universe requests the VMEbus and generates an IACK cycle. Once the
IACK cycle is complete, a PCI bus interrupt is generated to allow the proper Interrupt
Caution
Chapter 4 – Programming
4-5