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Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Manual page 38

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Chapter 1: VC7203 IBERT Getting Started Guide
16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then
X-Ref Target - Figure 1-32
38
Send Feedback
select the Debug Core Options tab in the Cell Properties window and change
C_USER_SCAN_CHAIN* to 2
Figure 1-32: Debug Core Options for dbg_hub
www.xilinx.com
(Figure
1-32). Click File > Save Constraints.
VC7203 IBERT Getting Started Guide
UG847 (v4.0) November 6, 2013

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