Viewing Gtx Transceiver Operation; Closing The Ibert Demonstration - Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Manual

Viewing GTX Transceiver Operation

After completing
configured and running. The status and test settings are displayed on the Links tab in the
Links window shown in
Note the line rate, TX differential output swing, and error count:
•
•
•
X-Ref Target - Figure 1-19
Additional information on the Vivado Design Suite software and IBERT core can be found
in Vivado Design Suite User Guide: Programming and Debugging (UG908) and LogiCORE IP
Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for Vivado
Design Suite (PG132).

Closing the IBERT Demonstration

To stop the IBERT demonstration:
1.
2.
VC7203 IBERT Getting Started Guide
UG847 (v4.0) November 6, 2013
step 6 in Starting the SuperClock-2
Figure
The line rate for all four GTX transceivers is 12.5 Gb/s (see Status in
The GTX transmitter differential output swing is preset to 850 mV.
Verify that there are no bit errors.
Figure 1-19: Serial I/O Analyzer Links
Close the Vivado Design Suite application by selecting File > Exit.
Place the main power switch SW1 in the off position.
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Running the GTX IBERT Demonstration
Module, the IBERT demonstration is
1-19.
Figure 1-19).
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