Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Manual page 32

Chapter 1: VC7203 IBERT Getting Started Guide
9.
X-Ref Target - Figure 1-26
32
Send Feedback
In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter E19 for P
Package Pin and E18 for N Package Pin (the FPGA pins that the system clock connects
to), and make sure the Frequency is set to 200.00
Output Products window opens. Leave the defaults unchanged, and press Generate.
Figure 1-26: Customize IP - Clock Settings
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(Figure 1-26). Press OK. A Generate
VC7203 IBERT Getting Started Guide
UG847 (v4.0) November 6, 2013