Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Manual page 20

Chapter 1: VC7203 IBERT Getting Started Guide
X-Ref Target - Figure 1-16
20
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Drag these signals from the Debug Probes window to the VIO Probes window
(Figure 1-16).
Note:
The ROM address values for the Si5368 and Si570 devices (that is, si5368_addr[6:0]
and si570_addr[6:0]) are preset to 60 to produce an output frequency of 156.250 MHz. Entering
a different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2, page 24.
Figure 1-16: SuperClock-2 Module VIO Core
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UG847 (v4.0) November 6, 2013