Revision History - Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Manual

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Revision History

The following table shows the revision history for this document.
Date Version
11/07/2012 1.0
01/23/2013 2.0
07/10/2013 3.0
11/06/2013 4.0
VC7203 IBERT Getting Started Guide
Initial Xilinx release.
Updated for ISE® Design Suite 14.4 and Vivado® Design Suite 2012.4.
Updated for Vivado Design Suite 2013.2. Updated
Launching the Vivado Design Suite Software, page
Module, page 16, and Creating the GTX IBERT Core, page 25
Updated for Vivado® Design Suite 2013.3. Device number was corrected from
XC7V485T to XC7VX485T. Updated most figures in
Started Guide. The ZIP project file name changed to
rdf0272-vc7203-ibert-2013-3.zip. In
to Xilinx TCF agent. Figure 1-30
Synthesize Out-Of-Context Module was deleted. Updated
Resources links.
www.xilinx.com
Revision
Extracting the Project Files, page
14, Starting the SuperClock-2
Chapter 1, VC7203 IBERT Getting
Figure 1-11, Digilent JTAG cable changed
was renamed Design Sources File Hierarchy. Figure 1-31,
Appendix A, Additional
UG847 (v4.0) November 6, 2013
7,
for the latest procedures.