Tektronix AWG5200 Series Technical Reference page 30

Specifications
Table 24: Trigger Inputs (cont.)
Characteristics
Delay to analog output
Asynchronous trigger mode
Synchronous trigger mode
Hold off
Jitter, asynchronous mode
1 kΩ selected
50 Ω selected
Jitter, synchronous mode
Trigger synchronized to
Internal or Ext Clock
Trigger synchronized to
Variable Reference
Trigger synchronized to Fixed
10 MHz Reference
18
Description
The DAC sampling clock frequency is displayed on the clock settings tab when the external
clock output is enabled.
8760/ fclk +68 ns ± 20 ns.
(1.820 μs at 5 GS/s)
(3.572 μs at 5 GS/s)
fclk is the frequency of the DAC sampling clock. The DAC sampling clock frequency is
displayed on the clock settings tab when the external clock output is enabled.
8275 / fclk + 30 ns ±20 ns
(1.685 μs at 5 GS/s.)
(3.340 μs at 2.5 GS/s.)
fclk is the frequency of the DAC sampling clock. The DAC sampling clock frequency is
displayed on the clock settings tab when the external clock output is enabled.
>2 μs
Trigger hold off is the amount of delay required at the end of a waveform before another trigger
pulse can be processed.
The asynchronous jitter performance is directly proportional the frequency of the DAC sampling
clock. The DAC sampling clock frequency is displayed on the clock settings tab when the
external clock output is enabled.
440 ps for 2.5 GHz DAC sampling clock.
p-p
240 ps for 5 GHz DAC sampling clock.
p-p
420 ps , 24 ps for 2.5 GHz DAC sampling clock.
p-p rms
220 ps , 14 ps for 5 GHz DAC sampling clock.
p-p rms
300 fs
rms
400 fs
rms
1.7 ps
rms
AWG5200 Series Technical Reference