GigaDevice Semiconductor GD32EPRT MCU Manuals

Manuals and User Guides for GigaDevice Semiconductor GD32EPRT MCU. We have 2 GigaDevice Semiconductor GD32EPRT MCU manuals available for free PDF download: User Manual

GigaDevice Semiconductor GD32EPRT User Manual (1334 pages)

Arm Cortex-M33 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 11 MB

Table of Contents
2
List of Figures
21
List of Tables
32
System and Memory Architecture
37
Arm ® Cortex ® -M33 Processor
37
Figure 1-1. the Structure of the Cortex ® -M33 Processor
37
System Architecture
38
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
38
Figure 1-2. High Density Devices System Architecture
40
Memory Map
41
Figure 1-3. Connectivity Line Devices System Architecture
41
Table 1-2. Memory Map of Gd32E51X Devices
42
On-Chip SRAM Memory
45
On-Chip Flash Memory Overview
45
Boot Configuration
46
Device Electronic Signature
46
Table 1-3. Boot Modes
46
Memory Density Information
47
Unique Device ID (96 Bits)
47
System Configuration Registers
48
Flash Memory Controller (FMC)
49
Overview
49
Characteristics
49
Function Overview
49
Flash Memory Architecture
49
Table 2-1. Gd32E51X_Hd and Gd32E51X_Cl Base Address and Size for Flash Memory
49
Error Checking and Correcting (ECC)
50
Read Operations
51
Table 2-2. the Relation between WSCNT and AHB Clock Frequency
51
Unlock the FMC_CTL Register
52
Page Erase
53
Mass Erase
54
Figure 2-1. Process of Page Erase Operation
54
Main Flash Programming
55
Figure 2-2. Process of Mass Erase Operation
55
OTP Programming
57
Option Bytes Erase
57
Figure 2-3. Process of Word Program Operation
57
Option Bytes Programming
58
Option Bytes Description
58
Table 2-3. Option Bytes
59
Page Erase / Program Protection
60
Security Protection
60
Table 2-4. OB_WP Bit for Pages Protected
60
Register Definition
62
Wait State Register (FMC_WS)
62
Unlock Key Register (FMC_KEY)
63
Option Byte Unlock Key Register (FMC_OBKEY)
63
Status Register (FMC_STAT)
64
Control Register (FMC_CTL)
64
Address Register (FMC_ADDR)
66
ECC Control and Status Register (FMC_ECCCS)
66
Option Byte Status Register (FMC_OBSTAT)
68
Erase/Program Protection Register (FMC_WP)
68
Product ID Register (FMC_PID)
69
Backup Registers (BKP)
70
Overview
70
Characteristics
70
Function Overview
70
RTC Clock Calibration
70
Tamper Detection
70
Register Definition
72
Backup Data Register X (Bkp_Datax) (X= 0
72
RTC Signal Output Control Register (BKP_OCTL)
72
Tamper Pin Control Register (BKP_TPCTL)
73
Tamper Control and Status Register (BKP_TPCS)
74
Power Management Unit (PMU)
75
Overview
75
Characteristics
75
Function Overview
75
Backup Domain
76
Figure 4-1. Power Supply Overview
76
VDD / V Dda
77
Figure 4-2. Waveform of the BOR
77
Figure 4-3. Waveform of the por / PDR
78
Power Domain
79
Figure 4-4. Waveform of the LVD Threshold
79
Power Saving Modes
80
Table 4-1. Power Saving Mode Summary
83
Register Definition
85
Control Register 0 (PMU_CTL0)
85
Control and Status Register 0 (PMU_CS0)
87
Control Register 1 (PMU_CTL1)
89
Control and Status Register 1 (PMU_CS1)
90
Reset and Clock Unit (RCU)
91
High Density Reset and Clock Control Unit (RCU)
91
Reset Control Unit (RCTL)
91
Overview
91
Function Overview
91
Clock Control Unit (CCTL)
92
Overview
92
Figure 5-1. the System Reset Circuit
92
Figure 5-2. Clock Tree
93
Characteristics
94
Function Overview
94
Figure 5-3. HXTAL Clock Source
95
Figure 5-4. HXTAL Clock Source in Bypass Mode
95
Table 5-1. Clock Output 0 Source Select
98
Table 5-2. 1.1V Domain Voltage Selected in Deep-Sleep Mode
98
Register Definition
99
Control Register (RCU_CTL)
99
Clock Configuration Register 0 (RCU_CFG0)
100
Clock Interrupt Register (RCU_INT)
104
APB2 Reset Register (RCU_APB2RST)
106
APB1 Reset Register (RCU_APB1RST)
109
AHB Enable Register (RCU_AHBEN)
113
APB2 Enable Register (RCU_APB2EN)
114
APB1 Enable Register (RCU_APB1EN)
117
Backup Domain Control Register (RCU_BDCTL)
120
Reset Source/Clock Register (RCU_RSTSCK)
122
AHB Reset Register (RCU_AHBRST)
123
Clock Configuration Register 1 (RCU_CFG1)
124
Deep-Sleep Mode Voltage Register (RCU_DSV)
125
Additional Clock Control Register (RCU_ADDCTL)
125
Additional Clock Interrupt Register (RCU_ADDINT)
126
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
127
Clock Configuration Register 2 (RCU_CFG2)
128
APB1 Additional Reset Register (RCU_ADDAPB1RST)
128
APB1 Additional Enable Register (RCU_ADDAPB1EN)
129
Connectivity Line Devices: Reset and Clock Control Unit (RCU)
130
Reset Control Unit (RCTL)
130
Overview
130
Function Overview
130
Clock Control Unit (CCTL)
131
Overview
131
Figure 5-5. the System Reset Circuit
131
Figure 5-6. Clock Tree
132
Characteristics
133
Function Overview
134
Figure 5-7. HXTAL Clock Source
134
Figure 5-8. HXTAL Clock Source in Bypass Mode
134
Table 5-3. Clock Output 0 Source Select
137
Table 5-4. 1.1V Domain Voltage Selected in Deep-Sleep Mode
138
Register Definition
139
Control Register (RCU_CTL)
139
Clock Configuration Register 0 (RCU_CFG0)
141
Clock Interrupt Register (RCU_INT)
145
APB2 Reset Register (RCU_APB2RST)
148
APB1 Reset Register (RCU_APB1RST)
151
AHB Enable Register (RCU_AHBEN)
154
APB2 Enable Register (RCU_APB2EN)
156
APB1 Enable Register (RCU_APB1EN)
159
Backup Domain Control Register (RCU_BDCTL)
162
Reset Source/Clock Register (RCU_RSTSCK)
163
AHB Reset Register (RCU_AHBRST)
165
Clock Configuration Register 1 (RCU_CFG1)
166
Deep-Sleep Mode Voltage Register (RCU_DSV)
169
Additional Clock Control Register (RCU_ADDCTL)
170
Additional Clock Configuration Register (RCU_ADDCFG)
171
Additional Clock Interrupt Register (RCU_ADDINT)
172
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
173
Clock Configuration Register 2 (RCU_CFG2)
174
APB1 Additional Reset Register (RCU_ADDAPB1RST)
175
APB1 Additional Enable Register (RCU_ADDAPB1EN)
176
Clock Trim Controller (CTC)
177
Overview
177
Characteristics
177
Function Overview
177
REF Sync Pulse Generator
178
CTC Trim Counter
178
Figure 6-1. CTC Overview
178
Frequency Evaluation and Automatically Trim Process
179
Figure 6-2. CTC Trim Counter
179
Software Program Guide
180
Register Definition
182
Control Register 0 (CTC_CTL0)
182
Control Register 1 (CTC_CTL1)
183
Status Register (CTC_STAT)
184
Interrupt Clear Register (CTC_INTC)
186
Interrupt/Event Controller (EXTI)
188
Overview
188
Characteristics
188
Interrupts Function Overview
188
Table 7-1. NVIC Exception Types in Cortex ® -M33
189
Table 7-2. Interrupt Vector Table
189
External Interrupt and Event (EXTI) Block Diagram
193
External Interrupt and Event Function Overview
193
Figure 7-1. Block Diagram of EXTI
193
Hardware Trigger
194
Software Trigger
194
Table 7-3. EXTI Source
194
EXTI Register
196
Interrupt Enable Register (EXTI_INTEN)
196
Event Enable Register (EXTI_EVEN)
196
Rising Edge Trigger Enable Register (EXTI_RTEN)
197
Falling Edge Trigger Enable Register (EXTI_FTEN)
197
Software Interrupt Event Register (EXTI_SWIEV)
197
Pending Register (EXTI_PD)
198
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
199
Overview
199
Characteristics
199
Function Overview
199
GPIO Pin Configuration
200
Figure 8-1. Basic Structure of a General-Pupose I/O
200
Table 8-1. GPIO Configuration Table
200
External Interrupt/Event Lines
201
Alternate Functions (AF)
201
Input Configuration
201
Output Configuration
202
Analog Configuration
202
Figure 8-2. Basic Structure of Input Configuration
202
Figure 8-3. Basic Structure of Output Configuration
202
Alternate Function (AF) Configuration
203
IO Pin Function Selection
203
Figure 8-4. Basic Structure of Analog Configuration
203
Figure 8-5. Basic Structure of Alternate Function Configuration
203
GPIO Locking Function
204
GPIO I/O Compensation Cell
204
Remapping Function I/O and Debug Configuration
204
Introduction
204
Main Features
205
JTAG/SWD Alternate Function Remapping
205
Table 8-2. Debug Interface Signals
205
Table 8-3. Debug Port Mapping and Pin Availability
205
ADC AF Remapping
206
TIMER AF Remapping
206
Table 8-4. ADC0/1 External Trigger Routine Conversion AF Remapping Function
206
Table 8-5. Timerx Alternate Function Remapping
206
Table 8-6. TIMER4 Alternate Function Remapping
207
USART AF Remapping
208
I2C0 AF Remapping
208
Table 8-7. USART0/1/2 Alternate Function Remapping
208
SPI0/SPI2/I2S AF Remapping
209
CAN0/1 AF Remapping
209
Table 8-8. I2C0 Alternate Function Remapping
209
Table 8-9. SPI0/SPI2/I2S Alternate Function Remapping
209
Table 8-10. CAN0/1 Alternate Function Remapping
209
Ethernet AF Remapping
210
CTC AF Remapping
210
CLK Pins AF Remapping
210
Table 8-11. ENET Alternate Function Remapping
210
Table 8-12. CTC Alternate Function Remapping
210
Table 8-13. OSC32 Pins Configuration
211
Table 8-14. OSC Pins Configuration
211
Register Definition
212
Port Control Register 0 (Gpiox_Ctl0, X=A
212
Port Control Register 1 (Gpiox_Ctl1, X=A
214
Port Input Status Register (Gpiox_Istat, X=A
215
Port Output Control Register (Gpiox_Octl, X=A
216
Port Bit Operate Register (Gpiox_Bop, X=A
216
Port Bit Clear Register (Gpiox_Bc, X=A
217
Port Configuration Lock Register (Gpiox_Lock, X=A
217
Port Bit Speed Register (Gpiox_ SPD, X=A
218
Event Control Register (AFIO_EC)
219
AFIO Port Configuration Register 0 (AFIO_PCF0)
219
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
226
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
227
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
228
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
229
AFIO Port Configuration Register 1 (AFIO_PCF1)
231
IO Compensation Control Register (AFIO_CPSCTL)
232
AFIO Port Configuration Register a (AFIO_PCFA)
233
AFIO Port Configuration Register B (AFIO_PCFB)
235
AFIO Port Configuration Register C (AFIO_PCFC)
238
AFIO Port Configuration Register D (AFIO_PCFD)
240
AFIO Port Configuration Register E (AFIO_PCFE)
241
AFIO Port Configuration Register G (AFIO_PCFG)
242
Cyclic Redundancy Checks Management Unit (CRC)
245
Overview
245
Characteristics
245
Function Overview
246
Figure 9-1. Block Diagram of CRC Management Unit
246
Register Definition
248
Data Register (CRC_DATA)
248
Free Data Register (CRC_FDATA)
248
Control Register (CRC_CTL)
249
Initialization Data Register (CRC_IDATA)
249
Polynomial Register (CRC_POLY)
250
Trigonometric Math Unit (TMU)
251
Overview
251
Characteristics
251
Function Overview
251
TMU Block Diagram
251
Table 10-1. 9 Different Operation Modes
251
Data Format
252
Figure 10-1. Block Diagram of Trigonometric Math Unit
252
Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format
252
Mode 0 Description
253
Mode 1 Description
253
Table 10-3. Convert Per-Unit Values to Radians in Mode 0
253
Table 10-4. Convert Radians Values to Per-Unit Values in Mode 1
253
Mode 2 Description
254
Mode 3 Description
254
Mode 4 Description
255
Mode 5 Description
255
Mode 6 Description
255
Table 10-5. the Range of Input Value and R0 Value in Mode 5
255
Mode 7 Description
257
Figure 10-2. Calculation of R1 (Quadrant) and R0 (Ratio) Based on y and X Values
257
Table 10-6. the Condition of UDRF and OVRF Flag in Mode 6
257
Table 10-7. the Condition of UDRF and OVRF Flag in Mode 7
257
Mode 8 Description
258
Software Guideline
258
Figure 10-3. TMU Program Guidline
259
TMU Register
260
Input Data0 Register (TMU_IDATA0)
260
Input Data1 Register (TMU_IDATA1)
260
Control Register (TMU_CTL)
261
Data0 Register (TMU_DATA0)
262
Data1 Register (TMU_DATA1)
262
Status Register (TMU_STAT)
262
Direct Memory Access Controller (DMA)
264
Overview
264
Characteristics
264
Block Diagram
265
Function Overview
265
DMA Operation
265
Figure 11-1. Block Diagram of DMA
265
Table 11-1. DMA Transfer Operation
266
Peripheral Handshake
267
Arbitration
267
Figure 11-2. Handshake Mechanism
267
Address Generation
268
Circular Mode
268
Memory to Memory Mode
268
Channel Configuration
268
Interrupt
269
DMA Request Mapping
269
Figure 11-3. DMA Interrupt Logic
269
Table 11-2. Interrupt Events
269
Figure 11-4. DMA0 Request Mapping
270
Table 11-3. DMA0 Requests for each Channel
270
Figure 11-5. DMA1 Request Mapping
273
Table 11-4. DMA1 Requests for each Channel
273
Register Definition
274
Interrupt Flag Register (DMA_INTF)
274
Interrupt Flag Clear Register (DMA_INTC)
275
Channel X Control Register (Dma_Chxctl)
275
Channel X Counter Register (Dma_Chxcnt)
277
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
278
Channel X Memory Base Address Register (Dma_Chxmaddr)
278
Debug (DBG)
280
Introduction
280
JTAG/SW Function Description
280
Switch JTAG or SW Interface
280
Pin Assignment
280
JTAG Daisy Chained Structure
281
Debug Reset
281
JEDEC-106 ID Code
281
Debug Hold Function Description
281
Debug Support for Power Saving Mode
281
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
282
DBG Registers
283
ID Code Register (DBG_ID)
283
Control Register (DBG_CTL)
283
Analog-To-Digital Converter (ADC)
287
Introduction
287
Characteristics
287
Pins and Internal Signals
288
Figure 13-1. ADC Module Block Diagram (for ADC0 and ADC1)
288
Table 13-1. ADC Internal Input Signals
288
Table 13-2. ADC Input Pins Definition
288
Functional Overview
289
Foreground Calibration Function
290
Figure 13-2. ADC Module Block Diagram (for ADC2)
290
ADC Clock
291
ADCON Enable
291
Single-Ended and Differential Input Channels
291
Routine Sequence
292
Operation Modes
292
Figure 13-3. Single Operation Mode
292
Figure 13-4. Continuous Operation Mode
293
Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable
294
Figure 13-6. Scan Operation Mode, Continuous Operation Mode Enable
294
Figure 13-7. Discontinuous Operation Mode
294
Conversion Result Threshold Monitor
295
Data Storage Mode
295
Sample Time Configuration
296
External Trigger Configuration
296
Figure 13-8. 12-Bit Data Storage Mode
296
Figure 13-9. 6-Bit Data Storage Mode
296
Table 13-3. External Trigger Source for ADC0 and ADC1
296
DMA Request
297
ADC Internal Channels
297
Table 13-4. External Trigger Source for ADC2
297
Programmable Resolution (DRES)
298
On-Chip Hardware Oversampling
298
Table 13-5. T CONV Timings Depending on Resolution
298
Figure 13-10. 20-Bit to 16-Bit Result Truncation
299
Figure 13-11. Numerical Example with 5-Bits Shift and Rounding
299
Table 13-6. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)
299
ADC Sync Mode
300
Table 13-7. ADC Sync Mode Table
300
Free Mode
301
Routine Parallel Mode
301
Figure 13-12. ADC Sync Block Diagram
301
Routine Follow-Up Fast Mode
302
Routine Follow-Up Slow Mode
302
Figure 13-13. Routine Parallel Mode on 10 Channels
302
Figure 13-14. Routine Follow-Up Fast Mode on Routine Sequence (the CTN Bit of the Adcs Are Set)
302
ADC Interrupts
303
Figure 13-15. Routine Follow-Up Slow Mode on Routine Sequence Channel
303
ADC Registers
304
Status Register (ADC_STAT)
304
Control Register 0 (ADC_CTL0)
305
Control Register 1 (ADC_CTL1)
307
Sample Time Register 0 (ADC_SAMPT0)
309
Sample Time Register 1 (ADC_SAMPT1)
310
Watchdog High Threshold Register 0 (ADC_WDHT0)
311
Watchdog Low Threshold Register 0 (ADC_WDLT0)
311
Routine Sequence Register 0 (ADC_RSQ0)
311
Routine Sequence Register 1 (ADC_RSQ1)
312
Routine Sequence Register 2 (ADC_RSQ2)
313
Routine Data Register (ADC_RDATA)
313
Oversample Control Register (ADC_OVSAMPCTL)
314
Watchdog 1 Channel Selection Register (ADC_WD1SR)
315
Watchdog 2 Channel Selection Register (ADC_WD2SR)
316
Watchdog Threshold Register 1 (ADC_WDT1)
316
Watchdog Threshold Register 2 (ADC_WDT2)
317
Differential Mode Control Register (ADC_DIFCTL)
318
Digital-To-Analog Converter (DAC)
319
Overview
319
Characteristics
319
Figure 14-1. DAC Block Diagram
319
Table 14-1. DAC I/O Description
320
Table 14-2. DAC Triggers and Outputs Summary
320
Function Overview
321
DAC Enable
321
DAC Output Buffer
321
DAC Data Configuration
321
DAC Trigger
321
Table 14-3. Triggers of DAC
321
DAC Conversion
322
DAC Noise Wave
322
DAC Output Voltage
323
DMA Request
323
Figure 14-2. DAC LFSR Algorithm
323
Figure 14-3. DAC Triangle Noise Wave
323
DAC Concurrent Conversion
324
DAC Output FIFO
324
Register Definition
324
Dacx Control Register 0 (DAC_CTL0)
325
Dacx Software Trigger Register (DAC_SWT)
328
Dacx_Out0 12-Bit Right-Aligned Data Holding Register (DAC_OUT0_R12DH)
329
Dacx_Out0 12-Bit Left-Aligned Data Holding Register (DAC_OUT0_L12DH)
329
Dacx_Out0 8-Bit Right-Aligned Data Holding Register (DAC_OUT0_R8DH)
330
Dacx_Out1 12-Bit Right-Aligned Data Holding Register (DAC_OUT1_R12DH)
330
Dacx_Out1 12-Bit Left-Aligned Data Holding Register (DAC_OUT1_L12DH)
331
Dacx_Out1 8-Bit Right-Aligned Data Holding Register (DAC_OUT1_R8DH)
331
Dacx Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
332
Dacx Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
332
Dacx Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
333
Dacx_Out0 Data Output Register (DAC_OUT0_DO)
333
Dacx_Out1 Data Output Register (DAC_OUT1_DO)
334
Dacx Status Register 0 (DAC_STAT0)
334
Dacx Control Register 1 (DAC_CTL1)
335
Dacx Status Register 1 (DAC_STAT1)
336
Comparator (CMP)
338
Overview
338
Characteristics
338
Function Overview
338
CMP Clock
339
CMP I / O Configuration
339
Figure 15-1. CMP Block Diagram
339
CMP Register Write Protection
340
Table 15-1. CMP Inputs and Outputs Summary
340
CMP Output Blanking
341
Figure 15-2. the CMP Outputs Signal Blanking
341
Register Definition
342
CMP1 Control / Status Register (CMP1_CS)
342
CMP3 Control / Status Register (CMP3_CS)
344
CMP5 Control / Status Register (CMP5_CS)
345
Watchdog Timer (WDGT)
348

GigaDevice Semiconductor GD32EPRT User Manual (1245 pages)

Arm Cortex-M33 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 17 MB

Table of Contents
2
List of Figures
21
List of Tables
31
System and Memory Architecture
36
Arm ® Cortex ® -M33 Processor
36
Figure 1-1. the Structure of the Cortex ® -M33 Processor
36
System Architecture
37
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
37
Memory Map
39
Figure 1-2. Gd32E50X System Architecture
39
Table 1-2. Memory Map of Gd32E50X Devices
40
On-Chip SRAM Memory
43
On-Chip Flash Memory Overview
43
Boot Configuration
44
Device Electronic Signature
44
Table 1-3. Boot Modes
44
Memory Density Information
45
Unique Device ID (96 Bits)
45
System Configuration Registers
46
Flash Memory Controller (FMC)
47
Overview
47
Characteristics
47
Function Overview
47
Flash Memory Architecture
47
Table 2-1. Gd32E50X_Hd and Gd32E50X_Cl Base Address and Size for Flash Memory
47
Read Operations
48
Table 2-2. the Relation between WSCNT and AHB Clock Frequency
48
Unlock the FMC_CTL Register
49
Page Erase
50
Mass Erase
51
Figure 2-1. Process of Page Erase Operation
51
Main Flash Programming
52
Figure 2-2. Process of Mass Erase Operation
52
OTP Programming
54
Option Bytes Erase
54
Figure 2-3. Process of Word Program Operation
54
Option Bytes Modify
55
Option Bytes Description
55
Table 2-3. Option Bytes
56
Page Erase / Program Protection
57
Security Protection
57
Table 2-4. OB_WP Bit for Pages Protected
57
Register Definition
58
Wait State Register (FMC_WS)
58
Unlock Key Register (FMC_KEY)
59
Option Byte Unlock Key Register (FMC_OBKEY)
59
Status Register (FMC_STAT)
60
Control Register (FMC_CTL)
61
Address Register (FMC_ADDR)
62
Option Byte Status Register (FMC_OBSTAT)
62
Erase/Program Protection Register (FMC_WP)
63
Product ID Register (FMC_PID)
63
Backup Registers (BKP)
65
Overview
65
Characteristics
65
Function Overview
65
RTC Clock Calibration
65
Tamper Detection
65
Register Definition
67
Backup Data Register X (Bkp_Datax) (X= 0
67
RTC Signal Output Control Register (BKP_OCTL)
67
Tamper Pin Control Register (BKP_TPCTL)
68
Tamper Control and Status Register (BKP_TPCS)
69
Power Management Unit (PMU)
70
Overview
70
Characteristics
70
Function Overview
70
Figure 4-1. Power Supply Overview
70
Backup Domain
71
VDD / V Dda
72
Figure 4-2. Waveform of the por / PDR
72
Figure 4-3. Waveform of the BOR
73
Figure 4-4. Waveform of the LVD Threshold
74
1.1V Power Domain
75
Power Saving Modes
75
Table 4-1. Power Saving Mode Summary
78
Register Definition
80
Control Register 0 (PMU_CTL0)
80
Control and Status Register 0 (PMU_CS0)
82
Control Register 1 (PMU_CTL1)
84
Control and Status Register 1 (PMU_CS1)
85
Reset and Clock Unit (RCU)
86
High Density Reset and Clock Control Unit (RCU)
86
Reset Control Unit (RCTL)
86
Overview
86
Function Overview
86
Clock Control Unit (CCTL)
87
Overview
87
Figure 5-1. the System Reset Circuit
87
Figure 5-2. Clock Tree
88
Characteristics
89
Function Overview
89
Figure 5-3. HXTAL Clock Source
90
Figure 5-4. HXTAL Clock Source in Bypass Mode
90
Table 5-1. Clock Output 0 Source Select
93
Table 5-2. 1.1V Domain Voltage Selected in Deep-Sleep Mode
93
Register Definition
94
Control Register (RCU_CTL)
94
Clock Configuration Register 0 (RCU_CFG0)
95
Clock Interrupt Register (RCU_INT)
99
APB2 Reset Register (RCU_APB2RST)
101
APB1 Reset Register (RCU_APB1RST)
104
AHB Enable Register (RCU_AHBEN)
107
APB2 Enable Register (RCU_APB2EN)
108
APB1 Enable Register (RCU_APB1EN)
111
Backup Domain Control Register (RCU_BDCTL)
114
Reset Source/Clock Register (RCU_RSTSCK)
115
AHB Reset Register (RCU_AHBRST)
117
Clock Configuration Register 1 (RCU_CFG1)
118
Deep-Sleep Mode Voltage Register (RCU_DSV)
118
Additional Clock Control Register (RCU_ADDCTL)
119
Additional Clock Interrupt Register (RCU_ADDINT)
120
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
120
Clock Configuration Register 2 (RCU_CFG2)
121
APB1 Additional Reset Register (RCU_ADDAPB1RST)
122
APB1 Additional Enable Register (RCU_ADDAPB1EN)
122
Connectivity Line Devices: Reset and Clock Control Unit (RCU)
124
Reset Control Unit (RCTL)
124
Overview
124
Function Overview
124
Clock Control Unit (CCTL)
125
Overview
125
Figure 5-5. the System Reset Circuit
125
Figure 5-6. Clock Tree
126
Characteristics
127
Function Overview
128
Figure 5-7. HXTAL Clock Source
128
Figure 5-8. HXTAL Clock Source in Bypass Mode
128
Table 5-3. Clock Output 0 Source Select
131
Table 5-4. 1.1V Domain Voltage Selected in Deep-Sleep Mode
132
Register Definition
133
Control Register (RCU_CTL)
133
Clock Configuration Register 0 (RCU_CFG0)
135
Clock Interrupt Register (RCU_INT)
138
APB2 Reset Register (RCU_APB2RST)
142
APB1 Reset Register (RCU_APB1RST)
144
AHB Enable Register (RCU_AHBEN)
147
APB2 Enable Register (RCU_APB2EN)
149
APB1 Enable Register (RCU_APB1EN)
152
Backup Domain Control Register (RCU_BDCTL)
155
Reset Source/Clock Register (RCU_RSTSCK)
156
AHB Reset Register (RCU_AHBRST)
158
Clock Configuration Register 1 (RCU_CFG1)
159
Deep-Sleep Mode Voltage Register (RCU_DSV)
162
Additional Clock Control Register (RCU_ADDCTL)
162
Additional Clock Configuration Register (RCU_ADDCFG)
164
Additional Clock Interrupt Register (RCU_ADDINT)
165
PLL Clock Spread Spectrum Control Register (RCU_PLLSSCTL)
166
Clock Configuration Register 2 (RCU_CFG2)
167
APB1 Additional Reset Register (RCU_ADDAPB1RST)
168
APB1 Additional Enable Register (RCU_ADDAPB1EN)
168
Clock Trim Controller (CTC)
170
Overview
170
Characteristics
170
Function Overview
170
Figure 6-1. CTC Overview
170
REF Sync Pulse Generator
171
CTC Trim Counter
171
Frequency Evaluation and Automatically Trim Process
172
Figure 6-2. CTC Trim Counter
172
Software Program Guide
173
Register Definition
175
Control Register 0 (CTC_CTL0)
175
Control Register 1 (CTC_CTL1)
176
Status Register (CTC_STAT)
177
Interrupt Clear Register (CTC_INTC)
179
Interrupt/Event Controller (EXTI)
181
Overview
181
Characteristics
181
Interrupts Function Overview
181
Table 7-1. NVIC Exception Types in Cortex ® -M33
182
Table 7-2. Interrupt Vector Table
182
External Interrupt and Event (EXTI) Block Diagram
186
External Interrupt and Event Function Overview
186
Figure 7-1. Block Diagram of EXTI
186
Table 7-3. EXTI Source
186
EXTI Register
189
Interrupt Enable Register (EXTI_INTEN)
189
Event Enable Register (EXTI_EVEN)
189
Rising Edge Trigger Enable Register (EXTI_RTEN)
190
Falling Edge Trigger Enable Register (EXTI_FTEN)
190
Software Interrupt Event Register (EXTI_SWIEV)
190
Pending Register (EXTI_PD)
191
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
192
Overview
192
Characteristics
192
Function Overview
192
GPIO Pin Configuration
193
Figure 8-1. Basic Structure of a General-Pupose I/O
193
Table 8-1. GPIO Configuration Table
193
External Interrupt/Event Lines
194
Alternate Functions (AF)
194
Input Configuration
194
Figure 8-2. Basic Structure of Input Configuration
194
Output Configuration
195
Analog Configuration
195
Figure 8-3. Basic Structure of Output Configuration
195
Figure 8-4. Basic Structure of Analog Configuration
195
Alternate Function (AF) Configuration
196
IO Pin Function Selection
196
Figure 8-5. Basic Structure of Alternate Function Configuration
196
GPIO Locking Function
197
GPIO I/O Compensation Cell
197
Remapping Function I/O and Debug Configuration
197
Introduction
197
Main Features
197
JTAG/SWD Alternate Function Remapping
198
ADC AF Remapping
198
Table 8-2. Debug Interface Signals
198
Table 8-3. Debug Port Mapping and Pin Availability
198
Table 8-4. ADC0/1 External Trigger Routine Conversion AF Remapping Function
198
TIMER AF Remapping
199
Table 8-5. Timerx Alternate Function Remapping
199
USART AF Remapping
200
Table 8-6. TIMER4 Alternate Function Remapping
200
Table 8-7. USART0/1/2 Alternate Function Remapping
200
I2C0 AF Remapping
201
SPI0/SPI2/I2S AF Remapping
201
Table 8-8. I2C0 Alternate Function Remapping
201
CAN0/1 AF Remapping
202
Table 8-9. SPI0/SPI2/I2S Alternate Function Remapping
202
Table 8-10. CAN0/1 Alternate Function Remapping
202
Ethernet AF Remapping
203
CTC AF Remapping
203
CLK Pins AF Remapping
203
Table 8-11. ENET Alternate Function Remapping
203
Table 8-12. CTC Alternate Function Remapping
203
Table 8-13. OSC32 Pins Configuration
203
Table 8-14. OSC Pins Configuration
203
Register Definition
205
Port Control Register 0 (Gpiox_Ctl0, X=A
205
Port Control Register 1 (Gpiox_Ctl1, X=A
207
Port Input Status Register (Gpiox_Istat, X=A
208
Port Output Control Register (Gpiox_Octl, X=A
209
Port Bit Operate Register (Gpiox_Bop , X=A
209
Port Bit Clear Register (Gpiox_Bc, X=A
210
Port Configuration Lock Register (Gpiox_Lock, X=A
210
Port Bit Speed Register (Gpiox_ SPD, X=A
211
Event Control Register (AFIO_EC)
212
AFIO Port Configuration Register 0 (AFIO_PCF0)
212
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
219
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
220
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
221
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
222
AFIO Port Configuration Register 1 (AFIO_PCF1)
224
IO Compensation Control Register (AFIO_CPSCTL)
225
AFIO Port Configuration Register a (AFIO_PCFA)
226
AFIO Port Configuration Register B (AFIO_PCFB)
228
AFIO Port Configuration Register C (AFIO_PCFC)
230
AFIO Port Configuration Register D (AFIO_PCFD)
232
AFIO Port Configuration Register E (AFIO_PCFE)
233
AFIO Port Configuration Register G (AFIO_PCFG)
234
Cyclic Redundancy Checks Management Unit (CRC)
237
Overview
237
Characteristics
237
Figure 9-1. Block Diagram of CRC Management Unit
237
Function Overview
238
Register Definition
239
Data Register (CRC_DATA)
239
Free Data Register (CRC_FDATA)
239
Control Register (CRC_CTL)
240
Initialization Data Register (CRC_IDATA)
240
Polynomial Register (CRC_POLY)
241
Trigonometric Math Unit (TMU)
242
Overview
242
Characteristics
242
Function Overview
242
TMU Block Diagram
242
Table 10-1. 9 Different Operation Modes
242
Data Format
243
Figure 10-1. Block Diagram of Trigonometric Math Unit
243
Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format
243
Mode 0 Description
244
Mode 1 Description
244
Table 10-3. Convert Per-Unit Values to Radians in Mode 0
244
Table 10-4. Convert Radians Values to Per-Unit Values in Mode 1
244
Mode 2 Description
245
Mode 3 Description
245
Mode 4 Description
245
Mode 5 Description
246
Mode 6 Description
246
Table 10-5. the Range of Input Value and R0 Value in Mode 5
246
Figure 10-2. Calculation of R1 (Quadrant) and R0 (Ratio) Based on y and X Values
247
Table 10-6. the Condition of UDRF and OVRF Flag in Mode 6
247
Mode 7 Description
248
Mode 8 Description
248
Software Guideline
248
Table 10-7. the Condition of UDRF and OVRF Flag in Mode 7
248
Figure 10-3. TMU Program Guidline
249
TMU Register
250
Input Data0 Register (TMU_IDATA0)
250
Input Data1 Register (TMU_IDATA1)
250
Control Register (TMU_CTL)
251
Data0 Register (TMU_DATA0)
252
Data1 Register (TMU_DATA1)
252
Status Register (TMU_STAT)
252
Direct Memory Access Controller (DMA)
254
Overview
254
Characteristics
254
Block Diagram
255
Function Overview
255
DMA Operation
255
Figure 11-1. Block Diagram of DMA
255
Table 11-1. DMA Transfer Operation
256
Peripheral Handshake
257
Arbitration
257
Figure 11-2. Handshake Mechanism
257
Address Generation
258
Circular Mode
258
Memory to Memory Mode
258
Channel Configuration
258
Interrupt
259
DMA Request Mapping
259
Figure 11-3. DMA Interrupt Logic
259
Table 11-2. Interrupt Events
259
Figure 11-4. DMA0 Request Mapping
260
Table 11-3. DMA0 Requests for each Channel
260
Table 11-4. DMA1 Requests for each Channel
260
Figure 11-5. DMA1 Request Mapping
261
Register Definition
263
Interrupt Flag Register (DMA_INTF)
263
Interrupt Flag Clear Register (DMA_INTC)
264
Channel X Control Register (Dma_Chxctl)
264
Channel X Counter Register (Dma_Chxcnt)
266
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
267
Channel X Memory Base Address Register (Dma_Chxmaddr)
267
Debug (DBG)
269
Introduction
269
JTAG/SW Function Description
269
Switch JTAG or SW Interface
269
Pin Assignment
269
JTAG Daisy Chained Structure
270
Debug Reset
270
JEDEC-106 ID Code
270
Debug Hold Function Description
270
Debug Support for Power Saving Mode
270
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
271
DBG Registers
272
ID Code Register (DBG_ID)
272
Control Register (DBG_CTL)
272
Analog-To-Digital Converter (ADC)
276
Introduction
276
Characteristics
276
Pins and Internal Signals
277
Figure 13-1. ADC Module Block Diagram (for ADC0 and ADC1)
277
Table 13-1. ADC Internal Input Signals
277
Table 13-2. ADC Input Pins Definition
277
Functional Overview
278
Foreground Calibration Function
279
Figure 13-2. ADC Module Block Diagram (for ADC2)
279
ADC Clock
280
ADCON Enable
280
Single-Ended and Differential Input Channels
280
Routine Sequence
281
Operation Modes
281
Figure 13-3. Single Operation Mode
281
Figure 13-4. Continuous Operation Mode
282
Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable
283
Figure 13-6. Scan Operation Mode, Continuous Operation Mode Enable
283
Figure 13-7. Discontinuous Operation Mode
283
Conversion Result Threshold Monitor
284
Data Storage Mode
284
Figure 13-8. 12-Bit Data Storage Mode
284
Sample Time Configuration
285
External Trigger Configuration
285
Figure 13-9. 6-Bit Data Storage Mode
285
Table 13-3. External Trigger Source for ADC0 and ADC1
285
Table 13-4. External Trigger Source for ADC2
285
DMA Request
286
ADC Internal Channels
286
Programmable Resolution (DRES)
287
On-Chip Hardware Oversampling
287
Table 13-5. Tconv Timings Depending on Resolution
287
Figure 13-10. 20-Bit to 16-Bit Result Truncation
288
Figure 13-11. Numerical Example with 5-Bits Shift and Rounding
288
Table 13-6. Maximum Output Results for N and M Combimations
288
ADC Sync Mode
289
Table 13-7. ADC Sync Mode Table
289
Free Mode
290
Routine Parallel Mode
290
Figure 13-12. ADC Sync Block Diagram
290
Routine Follow-Up Fast Mode
291
Routine Follow-Up Slow Mode
291
Figure 13-13. Routine Parallel Mode on 10 Channels
291
Figure 13-14. Routine Follow-Up Fast Mode on Routine Sequence (the CTN Bit of the Adcs Are Set)
291
ADC Interrupts
292
Figure 13-15. Routine Follow-Up Slow Mode on Routine Sequence Channel
292
ADC Registers
293
Status Register (ADC_STAT)
293
Control Register 0 (ADC_CTL0)
294
Control Register 1 (ADC_CTL1)
296
Sample Time Register 0 (ADC_SAMPT0)
298
Sample Time Register 1 (ADC_SAMPT1)
299
Watchdog High Threshold Register 0 (ADC_WDHT0)
300
Watchdog Low Threshold Register 0 (ADC_WDLT0)
300
Routine Sequence Register 0 (ADC_RSQ0)
300
Routine Sequence Register 1 (ADC_RSQ1)
301
Routine Sequence Register 2 (ADC_RSQ2)
302
Routine Data Register (ADC_RDATA)
302
Oversample Control Register (ADC_OVSAMPCTL)
303
Watchdog 1 Channel Selection Register (ADC_WD1SR)
304
Watchdog 2 Channel Selection Register (ADC_WD2SR)
305
Watchdog Threshold Register 1 (ADC_WDT1)
305
Watchdog Threshold Register 2 (ADC_WDT2)
306
Differential Mode Control Register (ADC_DIFCTL)
307
Digital-To-Analog Converter (DAC)
308
Introduction
308
Main Features
308
Function Description
309
DAC Enable
309
DAC Output Buffer
309
Figure 14-1. DAC Block Diagram
309
Table 14-1. DAC I/O Description
309
DAC Data Configuration
310
DAC Trigger
310
DAC Workflow
310
Table 14-2. External Triggers of DAC
310
DAC Output FIFO
311
DAC Noise Wave
311
DAC Output Calculate
312
DMA Funtion
312
Figure 14-2. DAC LFSR Algorithm
312
Figure 14-3. DAC Triangle Noise Wave
312
DAC Concurrent Conversion
313
DAC Registers
314
Control Register 0 (DAC_CTL0)
314
Software Trigger Register (DAC_SWT)
317
DAC_OUT0 12-Bit Right-Aligned Data Holding Register (OUT0_R12DH)
317
DAC_OUT0 12-Bit Left-Aligned Data Holding Register (OUT0_L12DH)
318
DAC_OUT0 8-Bit Right-Aligned Data Holding Register (OUT0_R8DH)
318
DAC_OUT1 12-Bit Right-Aligned Data Holding Register (OUT1_R12DH)
319
DAC_OUT1 12-Bit Left-Aligned Data Holding Register (OUT1_L12DH)
319
DAC_OUT1 8-Bit Right-Aligned Data Holding Register (OUT1_R8DH)
320
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
320
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
321
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
321
DAC_OUT0 Data Output Register (OUT0_DO)
322

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