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Specifications
* Software selectable baud rate/bit tim ing up to lim itations of physical layer.
* Graphical Bit Tim e/Baud Rate Calculator
GM Class 2/ SA E J1850 VPW
* VPW Physical Layer capable of Tx and Rx operations in high speed m odes (MC33390)
* Software controlled peripheral based VPW generation
* Software m odifiable bit tim ing acceptance param eters
* Software m odifiable bit tim ing generation param eters
* Trigger generation based on network error or lost arbitration event
* Bad CRC generation
* 4x high speed m ode (lim ited sim ultaneous operations at 41.6 k-bits)
* Block transfer m ode
* Break generation
* Bad Message generation capable
UA RT/ISO9141/Keyword 2000 (ISO14230)
* K and L lines im plem ented
* UART Based state m achine
* Initialization waveform s including Fast Init, Five Baud, CARB and Custom
* Program m able tim ing param eters including inter-byte, TX inter-fram e, RX inter-fram e and initialization waveform s (0.5 m s resolution)
* Software selectable baud rate
* Sock et selectable pull up resistor on both K and L lines
* Jum per selectable pull up voltage either 5V or Battery
* K and L have software controlled transm it enable lines allowing m any different variants of UART or ISO 9141 com m unications including: Tx on L Rx on K; Tx and Rx on K; Tx on K and L and Rx on K
Ford SCP/ SA E J1850 PWM
* Dual BCC Design : LBCC Com m unications Protocol IC Tx /Rx with optional "Monitor Mode" perform ed by a additional processor
* Software setup of LBCC including the Node Address, Look up Table 1 and 2, and the Network Driver and Receive Control Register
* Software selectable SCP bit rate of 41.6 k bps or 83.3 k bps
* Dynam ic Node Address m ode: LBCC is reconfigured when a m essage to be transm itted has a different node address then previously configured
SA E J1708
* SAE J1708 Physical Layer
* Software setup of SAE J1708 param eters
neoVI Documentation - (C) Copyright 2000-2019 Intrepid Control Systems, Inc.
Last Update: Wednesday, June 04, 2014
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