Intrepid Control Systems neoVI Hardware Help page 45

Intrepid Hardware Help Theory of Operation
Interfacing, and 4) MISC signals 3 through 7.
The J1850 VPW software is software controlled peripheral based VPW generation. This m eans that the ISO /J PIC µController uses a tim ing peripheral to generate and receive variable pulse width (VPW ) waveform s. This allows
the neoVI device to create faults and analyze VPW waveform s that would not be possible with other protocol ICs. It also allows support of different in-fram e responses which cause incom patibilities between J1850 VPW protocol
ICs.
The ISO /UART section is very flex ible. The K and L lines have software controlled transm it enable lines allowing m any different variants of UART or ISO 9141 com m unications including: Tx on L Rx on K; Tx and Rx on K; Tx on K
and L and Rx on K.
The MISC signals contain four 10 bit analog inputs and one ex ternal wak e-up input.
Figure 6 - The ISO/J PIC µController Section
neoVI Documentation - (C) Copyright 2000-2019 Intrepid Control Systems, Inc.
Last Update: Thursday, July 09, 2009
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