Holtek TinyPower HT69F40A Manual page 115

HT69F30A/HT69F40A/HT69F50A
TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM
TM
10-bit STM Register Definitions – n=1 for HT69F30A and n=2 for HT69F40A
• TMnC0 Register
Bit 7
Name TnPAU
R/W R/W
P�R 0
TnPAU: TMn Counter Pause Control
Bit 7
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
TnCK2, TnCK1, TnCK0: Select TMn Counter clock
Bit 6~4
000: f
001: f
010: f
011: f
100: f
101: Reserved
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TMn. Selecting the
Reserved clock input will effectively disable the internal counter. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
f
SYS
can be found in the oscillator section.
Bit 3 TnON: TMn Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again. If the TM is in the Compare Match
Output Mode then the TM output pin will be reset to its initial condition, as specified
by the TnOC bit, when the TnON bit changes from low to high.
TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7
Bit 2~0
Comparator P Match Period
000: 1024 TMn clocks
001: 128 TMn clocks
010: 256 TMn clocks
011: 384 TMn clocks
100: 512 TMn clocks
101: 640 TMn clocks
110: 768 TMn clocks
111: 896 TMn clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter's highest three bits. The result of this
comparison can be selected to clear the internal counter if the TnCCLR bit is set to
zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.20
6 5
TnCK2 TnCK1 TnCK0
R/W R/W R/W
0 0
/4
SYS
SYS
/16
H
/64
H
SUB
is the system clock, while f and f
H
11�
4 3 2
Tn�N TnRP2 TnRP1
R/W R/W
0 0 0
are other internal clocks, the details of which
SUB
1 0
TnRP0
R/W R/W
0 0
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