Ente�Ing The Sleep0 Mode; Ente�Ing The Sleep1 Mode; Ente�Ing The Idle0 Mode - Holtek TinyPower HT69F40A Manual

HT69F30A/HT69F40A/HT69F50A
TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM
TM
Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the
WDT and LVD both off. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock and the f
"HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped as the WDT is disabled.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the
WDT or LVD on. When this instruction is executed under the conditions described above, the
following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction, but the WDT or LVD will remain with the clock source coming from the f
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting as the WDT is enabled and its clock source is
selected to come from the f
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the
FSYSON bit in SMOD1 register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction, but the f
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting as the WDT clock source is derived from the f
clock.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.20
clock will be stopped and the application program will stop at the
SUB
clock.
SUB
clock will be on.
SUB
6�
clock.
SUB
SUB
��to�e� 0�� 201�