HT69F30A/HT69F40A/HT69F50A
TinyPower
I/O Flash 8-Bit MCU with LCD & EEPROM
TM
Time Base Interrupt
The function of the Time Base Interrupt is to provide regular time signal in the form of an internal
interrupt. It is controlled by the overflow signal from its internal timer. When this happens its
interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt
vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be
set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine
call to its respective vector location will take place. When the interrupt is serviced, the interrupt
request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other
interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source, f
TB
a divider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source which in turn
controls the Time Base interrupt period is selected using a bit in the TBC register.
TBC Register
Bit
7
Name
TB�N
R/W
R/W
P�R
0
Bit 7
TBON: Time Base 0 and Time Base 1 Enable/Disable
0: Disable
1: Enable
Bit 6
TBCK: TB Clock f
0: f
1: f
Bit 5~4
TB11~TB10: Time Base 1 Time-out Period Selection
00: 2
01: 2
10: 2
11: 2
Bit 3
LXTLP: LXT Low Power Control
0: Disable (LXT quick start-up)
1: Enable (LXT low power start-up)
Bit 2~0
TB02~TB00: Time Base 0 Time-out Period
000: 2
001: 2
010: 2
011: 2
100: 2
101: 2
110: 2
111: 2
L X T
L I R C
Rev. 1.20
, originates from the internal clock source f
6
5
TBCK
TB11
TB10
R/W
R/W
0
1
Select
TB
SUB
/4
SYS
/f
12
TB
/f
13
TB
/f
14
TB
/f
15
TB
/f
8
TB
/f
9
TB
/f
10
TB
/f
11
TB
/f
12
TB
/f
13
TB
/f
14
TB
/f
15
TB
f
/ 4
S Y S
M
M
f
U
U
f
S U B
X
X
C o n f i g u r a t i o n
T B C K B i t
O p t i o n
Time Base Interrupt
167
or f
/4. And then passes through
SUB
SYS
4
3
2
LXTLP
TB02
R/W
R/W
R/W
1
0
1
T B 0 2 ~ T B 0 0
¸
8
1 5
T i m e B a s e 0 I n t e r r u p t
2
~ 2
T B
¸
1 2
1 5
T i m e B a s e 1 I n t e r r u p t
2
~ 2
T B 1 1 ~ T B 1 0
1
0
TB01
TB00
R/W
R/W
1
1
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