Holtek TinyPower HT69F40A Manual page 60

TinyPower
HTO: High speed system oscillator ready flag
Bit 2
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to "0" by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as "1" by the application program after
device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after
a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if
the HXT oscillator is used.
bit 1 IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
bit 0 HLCLK: System clock selection
0: f
1: f
This bit is used to select if the f
the system clock. When the bit is high the f
f /2~f
H
to the f
SMOD1 Register
Bit 7
Name FSYS�N
R/W R/W
P�R 0
Bit 7 FSYSON: f
0: Disable
1: Enable
Bit 6~3 Unimplemented, read as "0"
Bit 2 LVRF: LVR function reset flag
0: Not occurred
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation occurs. This bit can
only be cleared to 0 by the application program.
Bit 1 LRF: LVR Control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register
values. This in effect acts like a software-reset function. This bit can only be cleared to
0 by the application program.
bit 0 WRF: WDT Control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Rev. 1.20
HT69F30A/HT69F40A/HT69F50A
I/O Flash 8-Bit MCU with LCD & EEPROM
TM
/2~f /64 or f
H H SUB
H
clock or the f
H
/64 or f clock will be selected. When system clock switches from the f
H SUB
clock and the f clock will be automatically switched off to conserve power.
SUB H
6 5 4
— — —
— — —
— — —
Control in IDLE Mode
SYS
60
/2~f /64 or f clock is used as
H H SUB
clock will be selected and if low the
H
3 2 1
— LVRF LRF
— R/W R/W
— x 0
"x" unknown
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clock
H
0
WRF
R/W
0