Holtek TinyPower HT69F40A Manual page 59

HT69F30A/HT69F40A/HT69F50A
TinyPower I/O Flash 8-Bit MCU with LCD & EEPROM
TM
IDLE1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the SMOD1 register is high. In the IDLE1 Mode
the system oscillator will be inhibited from driving the CPU but may continue to provide a clock
source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In
the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high
speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f
on.
Control Register
A register pair, SMOD and SMOD1, is used for overall control of the internal clocks within the
device.
SMOD Register
Bit
Name CKS2
R/W R/W
P�R
CKS2~CKS0: The system clock selection when HLCLK is "0"
Bit 7~5
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
These three bits are used to select which clock is used as the system clock source.
In addition to the system clock source the LIRC, a divided version of the high speed
system oscillator can also be chosen as the system clock source.
Bit 4 FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the f
initially used after the device wakes up. When the bit is high, the f
be used as a temporary system clock to provide a faster wake up time as the f
is available.
Bit 3 LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 1~2 clock cycles if the LIRC oscillator is used.
Rev. 1.20
7 6 5
CKS1 CKS0 FSTEN
R/W R/W
0 0 0
(f or f )
SUB LXT LIRC
(f or f )
SUB LXT LIRC
/64
H
/32
H
/16
H
/8
H
/4
H
/2
H
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4 3 2
LT� HT�
R/W R R
0 0 0
, will also be
S
1 0
IDLEN HLCLK
R/W R/W
1 1
clock source is
SUB
clock source can
SUB
clock
SUB
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