Definition Of Terms; Thermal Design Process - Intel 7512 Thermal/Mechanical Design Manuallines

Figure 1-1.

Thermal Design Process

S te p 1 : T h e r m a l
S im u la tio n
T h e r m a l M o d e l
T h e r m a l M o d e l U s e r's G u id e
1.2

Definition of Terms

FC-BGA
BLT
MB
T
case_max
T
case_min
TDP
8
S te p 2 : H e a ts in k S e le c tio n
T h e r m a l R e fe r e n c e
M e c h a n ic a l R e fe r e n c e
Flip Chip Ball Grid Array. A package type defined by a plastic substrate where
a die is mounted using an underfill C4 (Controlled Collapse Chip Connection)
attach style. The primary electrical interface is an array of solder balls
attached to the substrate opposite the die. Note that the device arrives at
the customer with solder balls attached.
Bond Line Thickness. Final settled thickness of the thermal interface
material after installation of heatsink.
Intel 7500 Scalable Memory Buffer. The chipset component responsible for
®
handling Intel Scalable Memory Interconnect (Intel
memory requests to and from the local DIMM. All memory control for the
DRAM resides in the host, including memory request initiation, timing,
refresh, scrubbing, sparing, configuration access, and power management.
Maximum die operating temperature, and is measured at the geometric
center of the top of the die.
Minimum die operating temperature, and is measured at the geometric
center of the top of the die.
Thermal design power: Thermal solutions should be designed to dissipate
this target power level. TDP is not the maximum power that the chipset can
dissipate.
S te p 3 : T h e r m a l V a lid a tio n
T h e r m a l T e s tin g S o ftw a r e
S o ftw a re U s e r's G u id e
Intel® 7500, 7510, and 7512 Scalable Memory Buffer TMDG
Introduction
®
SMI) channel and