Reset Source; Boot Option; Table 6. Boot Related Switch - ST STM32091C-EVAL User Manual

Hardware Layout and configuration
SB14
2.5

Reset Source

The reset signal of STM32091C-EVAL evaluation board is low active and the reset sources
include:
• Reset button B1
•
Debugging Tools from SWD connector CN10 and CN11
• Daughter board from CN7
•
Embedded ST-LINK/V2-1
• RS232 connector CN9 for ISP.
Note: The jumper JP11 to be closed for RESET handled by pin8 of RS232 connector CN9 (CTS
signal), refer to
2.6

Boot Option

The STM32091C-EVAL evaluation board is able to boot from:
•
Embedded User Flash
•
System memory with boot loader for ISP
•
Embedded SRAM for debugging
The boot option is configured by setting one jumper cap on CN7 between pin 22 and pin 24
and one Option bit.
Switch
configuration
CN7 pin 22 and
pin 24 open
CN7 pin 22 and
pin 24 close by
jumper
CN7 pin 22 and
pin 24 close by
jumper
The BOOT0 can be also configured via RS232 connector CN9, as shown in
16/58
Table 5. 8MHz Crystal X2 related Solder Bridges (continued)
PF1 is connected to 8MHz crystal when SB14 is open.
(Default setting)
PF1 is connected to extension connector CN7 when SB14 is closed. In such case
R56 must be removed to avoid disturbance due to the 8Mhz quartz.
Section 2.8 for details.

Table 6. Boot related Switch

bit12 in USER
OPTION BYTES
X
0
1
DocID026902 Rev 2
STM32091C-EVAL boot from User Flash. (Default setting)
STM32091C-EVAL boot from Embedded SRAM.
STM32091C-EVAL boot from System Memory.
Boot from
Table
UM1817
7.