Ssram - Altera Cyclone III Reference Manual

Table 2–14. DDR SDRAM Pinout (Part 3 of 3)
Signal Name
V14
ddr_dq15
Note to Table 2–14:
(1) The Cyclone III EP3C25F324 only supports one I/O standard in an I/O bank. I/O banks 3 and 4 are shared among
the DDR, HSMC and LEDs. In several DDR designs, some of the I/O pins that share the same banks with the DDR
are unavailable for use due to different I/O standards. Therefore, if you have added DDR to your system, I/O
banks 3 and 4 is to be configured as SSTL-2 only while the HSMC and LEDs pins which are not using SSTL-2,
should be removed.
Table 2–15. SSRAM Manufacturing Information
Board Reference
U5 256K x 32 synchronous SRAM
Table 2–16. SSRAM Pinout (Part 1 of 3)
Signal Name
A16
flash_sram_a2
B16
flash_sram_a3
A15
flash_sram_a4
B15
flash_sram_a5
A14
flash_sram_a6
B14
flash_sram_a7
A13
flash_sram_a8
B13
flash_sram_a9
A12
flash_sram_a10
B12
flash_sram_a11
A11
flash_sram_a12
B11
flash_sram_a13
Altera Corporation
April 2012
Note (1)
FPGA Pin Direction
Bidirectional

SSRAM

The Cyclone III FPGA starter board has a 256K x 32 synchronous SRAM.
Table 2–15 lists SSRAM board reference and manufacturing
information.
Description
Table 2–16 shows the SSRAM signal name, corresponding FPGA pin,
signal direction, type, and board reference U5 SSRAM pin.
FPGA Pin Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Board Components and Interfaces
Type
SSTL-2
Manufacturer Manufacturer Part Number
Integrated Silicon IS61LPS25636A-200TQL1
Solutions, Inc.
Type
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
Cyclone III FPGA Starter Board Reference Manual
U4 (DDR) Pin
65
U5 (SSRAM) Pin
37
36
35
34
33
32
44
45
46
47
48
49
2–17