Clocking Circuitry - Altera Cyclone III Reference Manual

Clocking Circuitry

f
Clocking
Circuitry
2–6
Cyclone III FPGA Starter Board Reference Manual
Table 2–3 lists the Cyclone III EP3C25F324 device pin count.
Table 2–3. Cyclone III Device Pin Count
Board Component
SRAM/flash (shared bus)
SDRAM (DDR)
Push-buttons
LEDs
USB-Blaster/configuration
HSMC
Total Pins Used
Total EP3C25F324 pins
Unused pins
Notes to Table 2–3:
(1) The Cyclone III EP3C25F324 only supports one I/O standard in an I/O bank. I/O
banks 3 and 4 are shared among the DDR, HSMC and LEDs.
(2) In several DDR designs, some of the I/O pins that share the same banks with the
DDR are unavailable for use due to different I/O standards. Therefore, if you
have added DDR to your system, I/O banks 3 and 4 is to be configured as SSTL-2
only while the HSMC and LEDs pins which are not using SSTL-2, should be
removed.
You can configure the Cyclone III device via the on-board USB-Blaster
through the JTAG interface using an external programming cable (sold
separately).
For additional information about Altera devices, go to
www.altera.com/products/devices.
The Cyclone III FPGA starter board's clocking circuitry is designed to be
simple and easy to use. A single 50-MHz clock input is used and all other
clocks are generated using the Cyclone III device's phase-locked loops
(PLLs). The dedicated PLLs are used to distribute the flash, SSRAM, and
HSMC clocks.
Table 2–4 shows the clock pinout.
Table 2–4. Clock Pinout
Signal Name
50 MHz B9, V9
72
(1) (2)
42
4
4 (1)
4
(1)
84
210
214
4
FPGA Pin Direction
Input
Pins
or
™
Type
2.5 V
Altera Corporation
April 2012