Ddr Sdram - Altera Cyclone III Reference Manual

Table 2–12. Parallel Flash Memory Pinout (Part 3 of 3)
Signal Name
flash_sram_dq13
flash_sram_dq14
flash_sram_dq15
flash_we_n
flash_ce_n
flash_oe_n
flash_reset_n
flash_adv_n
flash_clk (dclk)
flash_wait
Table 2–13. DDR SDRAM Manufacturing Information
Board Reference
U4 4M x16 x 4 DDR SDRAM
Table 2–14. DDR SDRAM Pinout (Part 1 of 3)
Signal Name
U3
ddr_dqs0
T8
ddr_dqs1
V3
ddr_dm0
V8
ddr_dm1
V11
ddr_ba0
V12
ddr_ba1
T4
ddr_cas_n
Altera Corporation
April 2012
FPGA Pin
B5 Bidirectional
A5 Bidirectional
B6 Bidirectional
D18 Output
E2 Output
D17 Output
C3 Output
H14 Output
H4 Output
H13 Output

DDR SDRAM

The Cyclone III FPGA starter board has a 4M x 16 x 4 DDR SDRAM.
Table 2–13 lists DDR SDRAM board reference and manufacturing
information.
Description
Table 2–14 shows the DDR SDRAM signal name, corresponding FPGA
pin, signal direction, type, and board reference U4 DDR pin.
Note (1)
FPGA Pin
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Board Components and Interfaces
Direction
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
Manufacturer
PowerChip
Semiconductor
Direction Type
SSTL-2
SSTL-2
SSTL-2
SSTL-2
SSTL-2
SSTL-2
SSTL-2
Cyclone III FPGA Starter Board Reference Manual
Type U6 (Flash) Pin
H5
G7
E7
G8
B4
F8
D4
F6
E6
F7
Manufacturer Part Number
A2S56D40CTP-G5PP
U4 (DDR) Pin
16
51
47
20
26
27
22
2–15