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Summary of Contents for Altera CPLD
- Page 1 Thank you for choosing as the hurricane core development board - learning board www.sz-21eda.com Translated without permission by organicmonkeymotion.wordpress.com V1 11/01/2014 Altera CPLD learning board manual QQ:906606596...
- Page 2 Thank you for choosing as the hurricane core development board - learning board www.sz-21eda.com Translated without permission by organicmonkeymotion.wordpress.com V1 11/01/2014 Contents Development board intended use ......................3 Development board hardware description ..................3 Hardware Circuit Description ......................4 Power .............................. 4 Clock ...............................
- Page 3 The development board provides a JTAG interface for programming the chip. Programming by ByteBlasterII download cable is recommended is it can download to FPGA / CPLD chips by Altera Corporation. The development board has 65 I / O ports are cited by pin outs marked on the board. The user can configure the pin assignments.
- Page 4 Use an external 5V DC power supply. Please note that the polarity of an external 5V DC power supply is positive (+ve) with respect to center. Clock CPLD (pin) P12 is provided with the 50M Hz clock frequency of the active crystal U3. I/O ports I / O ports are assigned as follows:...
- Page 5 Thank you for choosing as the hurricane core development board - learning board www.sz-21eda.com Translated without permission by organicmonkeymotion.wordpress.com V1 11/01/2014 I / O ports are assigned as follows: D30: P51 D34: P55 When the I / O port is low LED will be lit D31: P52 D35: P56 D32: P53...
- Page 6 Thank you for choosing as the hurricane core development board - learning board www.sz-21eda.com Translated without permission by organicmonkeymotion.wordpress.com V1 11/01/2014 Buzzer Drive P50 low to make noise with Buzzer. General headers I/O is also brought out to general headers JP1, JP2 and JP3.
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